[llvm] 962f3e4 - [Hexagon] Use the correct call to detect debug instructions (#83373)

[via llvm-commits]

Author: Sumanth Gundapaneni
Date: 2024-02-29T09:51:52-06:00
New Revision: 962f3e4e5bbdbfacb8c857a15013dae09bc49956

URL: https://github.com/llvm/llvm-project/commit/962f3e4e5bbdbfacb8c857a15013dae09bc49956
DIFF: https://github.com/llvm/llvm-project/commit/962f3e4e5bbdbfacb8c857a15013dae09bc49956.diff

LOG: [Hexagon] Use the correct call to detect debug instructions (#83373)

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
    llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 3b8234c0118435..4c18e076c43936 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1002,7 +1002,7 @@ namespace {
 bool DeadCodeElimination::isDead(unsigned R) const {
   for (const MachineOperand &MO : MRI.use_operands(R)) {
     const MachineInstr *UseI = MO.getParent();
-    if (UseI->isDebugValue())
+    if (UseI->isDebugInstr())
       continue;
     if (UseI->isPHI()) {
       assert(!UseI->getOperand(0).getSubReg());

diff  --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index e38c8bacaf2bab..56472d633694ae 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -1180,7 +1180,7 @@ void HexagonPacketizerList::unpacketizeSoloInstrs(MachineFunction &MF) {
       bool InsertBeforeBundle;
       if (MI.isInlineAsm())
         InsertBeforeBundle = !hasWriteToReadDep(MI, *BundleIt, HRI);
-      else if (MI.isDebugValue())
+      else if (MI.isDebugInstr())
         InsertBeforeBundle = true;
       else
         continue;