[llvm] [RISCV] Support scheduling VCIX instructions (PR #83427)

[Wang Pengcheng via llvm-commits]

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/83427

If we don't do anything, the latencies of VCIX instructions will be
all 1.

Here I just set the latency to a very large number, so the scheduler
will treat them costly.

Though I still don't know why scheduler doesn't take register presure
into consideration.

>From 03b6cebb7806a950bfa02963349830b393410c2a Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Thu, 29 Feb 2024 21:33:15 +0800
Subject: [PATCH] [RISCV] Support scheduling VCIX instructions

If we don't do anything, the latencies of VCIX instructions will be
all 1.

Here I just set the latency to a very large number, so the scheduler
will treat them costly.

Though I still don't know why scheduler doesn't take register presure
into consideration.
---
 llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 040cec42674000..2e7bd78f167e5f 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -1207,6 +1207,10 @@ foreach mx = SchedMxList in {
     def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx  # "_E" # sew), 0>;
 }
 
+let Latency = 100 in
+def WriteVCIX : SchedWriteRes<[SiFive7VCQ, SiFive7VA]>;
+def : InstRW<[WriteVCIX], (instregex "PseudoVC_.*")>;
+
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
 defm : UnsupportedSchedZabha;