[llvm] [AArch64] Re-enable rematerialization for streaming-mode-changing functions. (PR #83235)

[Sander de Smalen via llvm-commits]

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@@ -9494,40 +9494,12 @@ bool AArch64InstrInfo::isReallyTriviallyReMaterializable(
     // Avoid rematerializing rematerializable instructions that use/define
     // scalable values, such as 'pfalse' or 'ptrue', which result in different
     // results when the runtime vector length is different.
-    const MachineRegisterInfo &MRI = MF.getRegInfo();
     const MachineFrameInfo &MFI = MF.getFrameInfo();
-    if (any_of(MI.operands(), [&MRI, &MFI](const MachineOperand &MO) {
-          if (MO.isFI() &&
-              MFI.getStackID(MO.getIndex()) == TargetStackID::ScalableVector)
-            return true;
-          if (!MO.isReg())
-            return false;
-
-          if (MO.getReg().isVirtual()) {
-            const TargetRegisterClass *RC = MRI.getRegClass(MO.getReg());
-            return AArch64::ZPRRegClass.hasSubClassEq(RC) ||
-                   AArch64::PPRRegClass.hasSubClassEq(RC);
-          }
-          return AArch64::ZPRRegClass.contains(MO.getReg()) ||
-                 AArch64::PPRRegClass.contains(MO.getReg());
+    if (any_of(MI.operands(), [&MFI](const MachineOperand &MO) {
+          return MO.isFI() &&
+                 MFI.getStackID(MO.getIndex()) == TargetStackID::ScalableVector;
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sdesmalen-arm wrote:

The instruction that is rematerialisable that doesn't use VG (but would need it) is ADDXri, as this is used to materialise a frame-address, which only happens after register allocation. I've updated the PR to handle those instructions specifically, rather than walking through all instructions and their operands.

The corresponding test is `@call_to_non_streaming_pass_sve_objects` in llvm/test/CodeGen/AArch64/sme-streaming-interface.ll.

https://github.com/llvm/llvm-project/pull/83235