[llvm] WIP: AMDGPU: Document more backend recognized attributes (PR #80239)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 29 01:55:50 PST 2024
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/80239
>From 66a0f7ab5dc5a58425307011d334eb9da0b3c302 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Wed, 31 Jan 2024 13:59:01 +0530
Subject: [PATCH 1/3] WIP: AMDGPU: Document more backend recognized attributes
---
llvm/docs/AMDGPUUsage.rst | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 6b2417143ca06c..ee4af9f51998e6 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -1312,6 +1312,31 @@ The AMDGPU backend supports the following LLVM IR attributes.
the frame. This is an internal detail of how LDS variables are lowered,
language front ends should not set this attribute.
+ "amdgpu-gds-size" Bytes expected to be allocated at the start of GDS memory at entry.
+
+ "amdgpu-git-ptr-high" The hard-wired high half of the address of the global information table
+ for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
+ current hardware only allows a 16 bit value.
+
+ "amdgpu-32bit-address-high-bits" Assumed high 32-bits for
+ 32-bit address spaces which are really truncated
+ 64-bit addresses (i.e., addrspace(6))
+
+ "amdgpu-color-export" Assumed 1 for :ref:`amdgpu_ps <amdgpu_ps>`, and 0 for other calling conventions.
+
+ "amdgpu-depth-export" ..TODO:: Describe.
+
+ "InitialPSInputAddr" ..TODO:: Describe.
+
+
+ "amdgpu-wave-priority-threshold" ..TODO:: Describe.
+
+ "amdgpu-memory-bound". Set internally by backend
+
+ "amdgpu-wave-limiter" Set internally by backend
+
+ "amdgpu-unroll-threshold" ..TODO:: Describe.
+
======================================= ==========================================================
Calling Conventions
@@ -1397,7 +1422,7 @@ The AMDGPU backend supports the following calling conventions:
``amdgpu_ls`` Used for AMDPAL vertex shader if tessellation is in use.
..TODO::
Describe.
-
+.. _amdgpu_ps:
``amdgpu_ps`` Used for Mesa/AMDPAL pixel shaders.
..TODO::
Describe.
>From 5d1f00204996f6d51d07ceb8c21764699b05bcf3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 29 Feb 2024 15:21:06 +0530
Subject: [PATCH 2/3] Add descriptions for graphics attrs
---
llvm/docs/AMDGPUUsage.rst | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 175424334a4d18..d94497878008d0 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -1424,12 +1424,19 @@ The AMDGPU backend supports the following LLVM IR attributes.
32-bit address spaces which are really truncated
64-bit addresses (i.e., addrspace(6))
- "amdgpu-color-export" Assumed 1 for :ref:`amdgpu_ps <amdgpu_ps>`, and 0 for other calling conventions.
+ "amdgpu-color-export" Indicates shader exports color information if set to 1.
+ Defaults to 1 for :ref:`amdgpu_ps <amdgpu_ps>`, and 0 for other calling
+ conventions. Determines the necessity and type of null exports when a shader
+ terminates early by killing lanes.
- "amdgpu-depth-export" ..TODO:: Describe.
-
- "InitialPSInputAddr" ..TODO:: Describe.
+ "amdgpu-depth-export" Indicates shader exports depth information if set to 1. Determines the
+ necessity and type of null exports when a shader terminates early by killing
+ lanes. A depth-only shader will export to depth channel when no null export
+ target is available (GFX11+).
+ "InitialPSInputAddr" Set the initial value of the `spi_ps_input_addr` register for
+ :ref:`amdgpu_ps <amdgpu_ps>` shaders. Any bits enabled by this value will
+ be enabled in the final register value.
"amdgpu-wave-priority-threshold" ..TODO:: Describe.
@@ -1437,7 +1444,9 @@ The AMDGPU backend supports the following LLVM IR attributes.
"amdgpu-wave-limiter" Set internally by backend
- "amdgpu-unroll-threshold" ..TODO:: Describe.
+ "amdgpu-unroll-threshold" Set base cost threshold preference for loop unrolling within this function,
+ default is 300. Actual threshold may be varied by per-loop metadata or
+ reduced by heuristics.
======================================= ==========================================================
>From 6b83c8c6ca474ce42da4baaef6446a42b2890531 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 29 Feb 2024 15:25:29 +0530
Subject: [PATCH 3/3] Try to describe amdgpu-wave-priority-threshold
---
llvm/docs/AMDGPUUsage.rst | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index d94497878008d0..4316058eb4c711 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -1438,7 +1438,10 @@ The AMDGPU backend supports the following LLVM IR attributes.
:ref:`amdgpu_ps <amdgpu_ps>` shaders. Any bits enabled by this value will
be enabled in the final register value.
- "amdgpu-wave-priority-threshold" ..TODO:: Describe.
+ "amdgpu-wave-priority-threshold" VALU instruction count threshold for adjusting wave priority. If exceeded,
+ temporarily raise the wave priority at the start of the shader function
+ until its last VMEM instructions to allow younger waves to issue their VMEM
+ instructions as well.
"amdgpu-memory-bound". Set internally by backend
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