[llvm] [Hexagon] Update the debug instruction call. (PR #83372)

via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 28 19:47:04 PST 2024


github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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You can test this locally with the following command:
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``````````bash
git-clang-format --diff 7d8b50aaab8e0f935e3cb1f3f397e98b9e3ee241 2a89fe144126959f60feb3e2c89aad54cd6ed569 -- llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 4b3b0142cc..4c18e076c4 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1003,7 +1003,7 @@ bool DeadCodeElimination::isDead(unsigned R) const {
   for (const MachineOperand &MO : MRI.use_operands(R)) {
     const MachineInstr *UseI = MO.getParent();
     if (UseI->isDebugInstr())
-        continue;
+      continue;
     if (UseI->isPHI()) {
       assert(!UseI->getOperand(0).getSubReg());
       Register DR = UseI->getOperand(0).getReg();

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https://github.com/llvm/llvm-project/pull/83372


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