[llvm] [RISCV] Add getFeaturesForCPU function support (PR #83269)

[Brandon Wu via llvm-commits]

https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/83269

>From 7ff111e220516010ec5e579fb942c50618cf9a89 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Wed, 28 Feb 2024 06:16:57 -0800
Subject: [PATCH 1/2] [RISCV] Add getFeaturesForCPU function support

This function parse the cpu and return it's supported
features placed in EnabledFeatures. It is same as the
one in X86TargetParser and also is used in IREE.
---
 .../llvm/TargetParser/RISCVTargetParser.h     |  3 +++
 llvm/lib/TargetParser/RISCVTargetParser.cpp   | 27 +++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index e7da677c7d3ead..553b4efe0e3038 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -25,6 +25,9 @@ namespace RISCV {
 // We use 64 bits as the known part in the scalable vector types.
 static constexpr unsigned RVVBitsPerBlock = 64;
 
+void getFeaturesForCPU(StringRef CPU,
+                       SmallVectorImpl<std::string> &EnabledFeatures,
+                       bool NeedPlus = false);
 bool parseCPU(StringRef CPU, bool IsRV64);
 bool parseTuneCPU(StringRef CPU, bool IsRV64);
 StringRef getMArchFromMcpu(StringRef CPU);
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 85cdd1289a9538..24a1e088d2df8b 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -14,6 +14,7 @@
 #include "llvm/TargetParser/RISCVTargetParser.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringSwitch.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/TargetParser/Triple.h"
 
 namespace llvm {
@@ -95,5 +96,31 @@ void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
 }
 
+void getFeaturesForCPU(StringRef CPU,
+                       SmallVectorImpl<std::string> &EnabledFeatures,
+                       bool NeedPlus) {
+  StringRef MarchFromCPU = llvm::RISCV::getMArchFromMcpu(CPU);
+  if (MarchFromCPU == "")
+    return;
+
+  EnabledFeatures.clear();
+  auto RII = RISCVISAInfo::parseArchString(
+      MarchFromCPU, /* EnableExperimentalExtension */ true);
+
+  if (llvm::errorToBool(RII.takeError()))
+    return;
+
+  std::vector<std::string> FeatStrings =
+      (*RII)->toFeatures(/* AddAllExtensions */ true);
+  for (const auto &F : FeatStrings) {
+    if (F[0] == '-')
+      continue;
+
+    if (NeedPlus)
+      EnabledFeatures.push_back(F);
+    else
+      EnabledFeatures.push_back(F.substr(1, F.size() - 1));
+  }
+}
 } // namespace RISCV
 } // namespace llvm

>From d9d877caa0a1f42c5715281fedb33c2233e0b8eb Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Wed, 28 Feb 2024 18:20:11 -0800
Subject: [PATCH 2/2] fixup! [RISCV] Add getFeaturesForCPU function support

---
 llvm/lib/TargetParser/RISCVTargetParser.cpp | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 24a1e088d2df8b..bdbd07d25d8384 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -96,6 +96,7 @@ void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
 #include "llvm/TargetParser/RISCVTargetParserDef.inc"
 }
 
+// This function is currently used by IREE, so it's not dead code.
 void getFeaturesForCPU(StringRef CPU,
                        SmallVectorImpl<std::string> &EnabledFeatures,
                        bool NeedPlus) {
@@ -111,16 +112,12 @@ void getFeaturesForCPU(StringRef CPU,
     return;
 
   std::vector<std::string> FeatStrings =
-      (*RII)->toFeatures(/* AddAllExtensions */ true);
-  for (const auto &F : FeatStrings) {
-    if (F[0] == '-')
-      continue;
-
+      (*RII)->toFeatures(/* AddAllExtensions */ false);
+  for (const auto &F : FeatStrings)
     if (NeedPlus)
       EnabledFeatures.push_back(F);
     else
       EnabledFeatures.push_back(F.substr(1, F.size() - 1));
-  }
 }
 } // namespace RISCV
 } // namespace llvm