[llvm] [llvm][CodeGen] Added a check in CodeGenPrepare::optimizeSwitchType (PR #83322)
Panagiotis K via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 28 16:03:04 PST 2024
https://github.com/karouzakisp updated https://github.com/llvm/llvm-project/pull/83322
>From b3302a5d60006129b830a24f14cce2e676807353 Mon Sep 17 00:00:00 2001
From: Panagiotis K <karouzakisp at gmail.com>
Date: Thu, 29 Feb 2024 00:02:05 +0000
Subject: [PATCH] [llvm][CodeGen] added check in
CodeGenPrepare::OptimizeSwitchType, so that if we have two users and
one of them is a SExt we don't use a ZExt in the Switch Condition
because that creates a redundant instruction.
---
llvm/lib/CodeGen/CodeGenPrepare.cpp | 14 +++-
llvm/test/CodeGen/RISCV/switch-width.ll | 107 +++++++++++++++++++++---
2 files changed, 108 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index feefe87f406365..c4dfa44bda5f70 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -7397,7 +7397,19 @@ bool CodeGenPrepare::optimizeSwitchType(SwitchInst *SI) {
if (Arg->hasZExtAttr())
ExtType = Instruction::ZExt;
}
-
+ // If Cond has 2 users and one of them is a sext don't use a zext.
+ bool HaveSExtUser = false;
+ if(Cond->hasNUses(2)){
+ for(auto &U : Cond->uses()){
+ Value *V = U.get();
+ if(isa<SExtInst>(V)){
+ HaveSExtUser = true;
+ }
+ }
+ }
+ if(HaveSExtUser){
+ ExtType = Instruction::SExt;
+ }
auto *ExtInst = CastInst::Create(ExtType, Cond, NewType);
ExtInst->insertBefore(SI);
ExtInst->setDebugLoc(SI->getDebugLoc());
diff --git a/llvm/test/CodeGen/RISCV/switch-width.ll b/llvm/test/CodeGen/RISCV/switch-width.ll
index d902bd3276a3ce..fa3a321d85c471 100644
--- a/llvm/test/CodeGen/RISCV/switch-width.ll
+++ b/llvm/test/CodeGen/RISCV/switch-width.ll
@@ -194,7 +194,90 @@ return:
%retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
ret i32 %retval
}
+define i32 @sext_i32(i16 %a) {
+; CHECK-LABEL: sext_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui a1, 16
+; CHECK-NEXT: addiw a1, a1, -1
+; CHECK-NEXT: and a2, a0, a1
+; CHECK-NEXT: beq a2, a1, .LBB5_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: slli a0, a0, 48
+; CHECK-NEXT: srai a0, a0, 48
+; CHECK-NEXT: li a1, 1
+; CHECK-NEXT: bne a0, a1, .LBB5_4
+; CHECK-NEXT: # %bb.2: # %sw.bb0
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB5_3: # %sw.bb1
+; CHECK-NEXT: li a0, 1
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB5_4: # %sw.default
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: ret
+entry:
+ %sext = sext i16 %a to i32
+ switch i32 %sext, label %sw.default [
+ i32 1, label %sw.bb0
+ i32 -1, label %sw.bb1
+ ]
+
+sw.bb0:
+ br label %return
+
+sw.bb1:
+ br label %return
+
+sw.default:
+ br label %return
+
+return:
+ %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
+ ret i32 %retval
+}
+
+define i32 @sext_i16(i8 %a) {
+; CHECK-LABEL: sext_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi a1, a0, 255
+; CHECK-NEXT: li a2, 255
+; CHECK-NEXT: beq a1, a2, .LBB6_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: slli a0, a0, 56
+; CHECK-NEXT: srai a0, a0, 56
+; CHECK-NEXT: slli a0, a0, 48
+; CHECK-NEXT: srli a0, a0, 48
+; CHECK-NEXT: li a1, 1
+; CHECK-NEXT: bne a0, a1, .LBB6_4
+; CHECK-NEXT: # %bb.2: # %sw.bb0
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB6_3: # %sw.bb1
+; CHECK-NEXT: li a0, 1
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB6_4: # %sw.default
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: ret
+entry:
+ %sext = sext i8 %a to i16
+ switch i16 %sext, label %sw.default [
+ i16 1, label %sw.bb0
+ i16 -1, label %sw.bb1
+ ]
+
+sw.bb0:
+ br label %return
+sw.bb1:
+ br label %return
+
+sw.default:
+ br label %return
+
+return:
+ %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
+ ret i32 %retval
+}
define i32 @trunc_i12(i64 %a) {
; CHECK-LABEL: trunc_i12:
@@ -202,17 +285,17 @@ define i32 @trunc_i12(i64 %a) {
; CHECK-NEXT: lui a1, 1
; CHECK-NEXT: addiw a1, a1, -1
; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: beq a0, a1, .LBB5_3
+; CHECK-NEXT: beq a0, a1, .LBB7_3
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: li a1, 1
-; CHECK-NEXT: bne a0, a1, .LBB5_4
+; CHECK-NEXT: bne a0, a1, .LBB7_4
; CHECK-NEXT: # %bb.2: # %sw.bb0
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB5_3: # %sw.bb1
+; CHECK-NEXT: .LBB7_3: # %sw.bb1
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB5_4: # %sw.default
+; CHECK-NEXT: .LBB7_4: # %sw.default
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: ret
entry:
@@ -241,17 +324,17 @@ define i32 @trunc_i11(i64 %a) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi a0, a0, 2047
; CHECK-NEXT: li a1, 2047
-; CHECK-NEXT: beq a0, a1, .LBB6_3
+; CHECK-NEXT: beq a0, a1, .LBB8_3
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: li a1, 1
-; CHECK-NEXT: bne a0, a1, .LBB6_4
+; CHECK-NEXT: bne a0, a1, .LBB8_4
; CHECK-NEXT: # %bb.2: # %sw.bb0
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB6_3: # %sw.bb1
+; CHECK-NEXT: .LBB8_3: # %sw.bb1
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB6_4: # %sw.default
+; CHECK-NEXT: .LBB8_4: # %sw.default
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: ret
entry:
@@ -281,17 +364,17 @@ define i32 @trunc_i10(i64 %a) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi a0, a0, 1023
; CHECK-NEXT: li a1, 1023
-; CHECK-NEXT: beq a0, a1, .LBB7_3
+; CHECK-NEXT: beq a0, a1, .LBB9_3
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: li a1, 1
-; CHECK-NEXT: bne a0, a1, .LBB7_4
+; CHECK-NEXT: bne a0, a1, .LBB9_4
; CHECK-NEXT: # %bb.2: # %sw.bb0
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB7_3: # %sw.bb1
+; CHECK-NEXT: .LBB9_3: # %sw.bb1
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB7_4: # %sw.default
+; CHECK-NEXT: .LBB9_4: # %sw.default
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: ret
entry:
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