[llvm] Spill/restore FP/BP around instructions in which they are clobbered (PR #81048)

[Reid Kleckner via llvm-commits]

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@@ -963,6 +963,16 @@ class TargetRegisterInfo : public MCRegisterInfo {
     return false;
   }
 
+  /// Returns true if the target needs a base register.
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rnk wrote:

I noticed that AArch64, PPC, ARM, and RISCV all use virtual base registers (requiresVirtualBaseRegisters returns true in most cases) instead of physical base registers. Should we look into that in addition to this change? Perhaps we can add an x86-specific cl::opt that uses a virtual base register, try that on some corpus of code, and see if that is a) correct and b) has acceptable performance.

Regardless, we still need support for spilling the FP around FP-clobbers, so I think we need your change, and we should go forward as is.

https://github.com/llvm/llvm-project/pull/81048