[llvm] [GISEL][RISCV] IRTranslator for scalable vector load (PR #80006)
Jiahan Xie via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 28 13:41:12 PST 2024
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@@ -483,6 +483,336 @@ define <vscale x 8 x i64> @vload_nx8i64(ptr %pa) {
; RV64-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 8 x s64>)
; RV64-NEXT: PseudoRET implicit $v8m8
%va = load <vscale x 8 x i64>, ptr %pa
- ret <vscale x 8 x i64> %va
+ ret <vscale x 8 x i64> %va
+}
+
+define <vscale x 1 x i8> @vload_nx1i8_align2(ptr %pa) {
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jiahanxie353 wrote:
You are right, I'll fix it!
https://github.com/llvm/llvm-project/pull/80006
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