[llvm] Apply the `AdjustICmpImmAndPred` optimization when it results in a one-instruction immediate materialization over a two-instruction materialization. (PR #83218)
Owen Anderson via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 28 12:10:47 PST 2024
https://github.com/resistor updated https://github.com/llvm/llvm-project/pull/83218
>From 011b120e820688b29f38426308a5db7f7d6de2d1 Mon Sep 17 00:00:00 2001
From: Owen Anderson <resistor at mac.com>
Date: Tue, 27 Feb 2024 22:19:50 -0500
Subject: [PATCH 1/2] Apply the `AdjustICmpImmAndPred` optimization when it
results in a one-instruction immediate materialization over a two-instruction
materialization.
https://github.com/llvm/llvm-project/issues/76460
---
.../GISel/AArch64PostLegalizerLowering.cpp | 12 +-
.../CodeGen/AArch64/GlobalISel/icmp-cst.ll | 185 ++++++++++++++++++
2 files changed, 193 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/icmp-cst.ll
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 9bc5815ae05371..96c97cb4706d55 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -588,7 +588,8 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
auto ValAndVReg = getIConstantVRegValWithLookThrough(RHS, MRI);
if (!ValAndVReg)
return std::nullopt;
- uint64_t C = ValAndVReg->Value.getZExtValue();
+ uint64_t OriginalC = ValAndVReg->Value.getZExtValue();
+ uint64_t C = OriginalC;
if (isLegalArithImmed(C))
return std::nullopt;
@@ -658,9 +659,12 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
// predicate if it is.
if (Size == 32)
C = static_cast<uint32_t>(C);
- if (!isLegalArithImmed(C))
- return std::nullopt;
- return {{C, P}};
+ if (isLegalArithImmed(C))
+ return {{C, P}};
+ if (AArch64_AM::isLogicalImmediate(C, Size) &&
+ !AArch64_AM::isLogicalImmediate(OriginalC, Size))
+ return {{C, P}};
+ return std::nullopt;
}
/// Determine whether or not it is possible to update the RHS and predicate of
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/icmp-cst.ll b/llvm/test/CodeGen/AArch64/GlobalISel/icmp-cst.ll
new file mode 100644
index 00000000000000..e6b27943372a83
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/icmp-cst.ll
@@ -0,0 +1,185 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -global-isel=1 < %s | FileCheck %s
+
+; CHECK-NOT: movk
+
+define dso_local noundef i1 @ule_11111111(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ult i32 %0, 286331154
+ ret i1 %2
+}
+
+define dso_local noundef i1 @ule_22222222(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ult i32 %0, 572662307
+ ret i1 %2
+}
+
+define dso_local noundef i1 @ule_33333333(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ult i32 %0, 858993460
+ ret i1 %2
+}
+
+define dso_local noundef i1 @ule_44444444(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ult i32 %0, 1145324613
+ ret i1 %2
+}
+
+define dso_local noundef i1 @ule_55555555(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ult i32 %0, 1431655766
+ ret i1 %2
+}
+
+define dso_local noundef i1 @ule_66666666(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ult i32 %0, 1717986919
+ ret i1 %2
+}
+
+define dso_local noundef i1 @ule_77777777(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ult i32 %0, 2004318072
+ ret i1 %2
+}
+
+define dso_local noundef i1 @ule_88888888(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ult i32 %0, -2004318071
+ ret i1 %2
+}
+
+define dso_local noundef i1 @ule_99999999(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ult i32 %0, -1717986918
+ ret i1 %2
+}
+
+define dso_local noundef i1 @uge_11111111(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ugt i32 %0, 286331152
+ ret i1 %2
+}
+
+define dso_local noundef i1 @uge_22222222(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ugt i32 %0, 572662305
+ ret i1 %2
+}
+
+define dso_local noundef i1 @uge_33333333(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ugt i32 %0, 858993458
+ ret i1 %2
+}
+
+define dso_local noundef i1 @uge_44444444(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ugt i32 %0, 1145324611
+ ret i1 %2
+}
+
+define dso_local noundef i1 @uge_55555555(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ugt i32 %0, 1431655764
+ ret i1 %2
+}
+
+define dso_local noundef i1 @uge_66666666(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ugt i32 %0, 1717986917
+ ret i1 %2
+}
+
+define dso_local noundef i1 @uge_77777777(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ugt i32 %0, 2004318070
+ ret i1 %2
+}
+
+define dso_local noundef i1 @uge_88888888(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ugt i32 %0, -2004318073
+ ret i1 %2
+}
+
+define dso_local noundef i1 @uge_99999999(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ugt i32 %0, -1717986920
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sle_11111111(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp slt i32 %0, 286331154
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sle_22222222(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp slt i32 %0, 572662307
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sle_33333333(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp slt i32 %0, 858993460
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sle_44444444(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp slt i32 %0, 1145324613
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sle_55555555(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp slt i32 %0, 1431655766
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sle_66666666(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp slt i32 %0, 1717986919
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sle_77777777(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp slt i32 %0, 2004318072
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sle_88888888(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ult i32 %0, -2004318071
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sle_99999999(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ult i32 %0, -1717986918
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sge_11111111(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp sgt i32 %0, 286331152
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sge_22222222(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp sgt i32 %0, 572662305
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sge_33333333(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp sgt i32 %0, 858993458
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sge_44444444(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp sgt i32 %0, 1145324611
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sge_55555555(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp sgt i32 %0, 1431655764
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sge_66666666(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp sgt i32 %0, 1717986917
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sge_77777777(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp sgt i32 %0, 2004318070
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sge_88888888(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ugt i32 %0, -2004318073
+ ret i1 %2
+}
+
+define dso_local noundef i1 @sge_99999999(i32 noundef %0) local_unnamed_addr #0 {
+ %2 = icmp ugt i32 %0, -1717986920
+ ret i1 %2
+}
+
+attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a,-fmv" }
\ No newline at end of file
>From ad38ae894bf80fdf20f765cb273c796aeefa0325 Mon Sep 17 00:00:00 2001
From: Owen Anderson <resistor at mac.com>
Date: Wed, 28 Feb 2024 15:10:28 -0500
Subject: [PATCH 2/2] Address feedback on testcase.
---
.../CodeGen/AArch64/GlobalISel/icmp-cst.ll | 185 -----
llvm/test/CodeGen/AArch64/icmp-cst.ll | 687 ++++++++++++++++++
2 files changed, 687 insertions(+), 185 deletions(-)
delete mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/icmp-cst.ll
create mode 100644 llvm/test/CodeGen/AArch64/icmp-cst.ll
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/icmp-cst.ll b/llvm/test/CodeGen/AArch64/GlobalISel/icmp-cst.ll
deleted file mode 100644
index e6b27943372a83..00000000000000
--- a/llvm/test/CodeGen/AArch64/GlobalISel/icmp-cst.ll
+++ /dev/null
@@ -1,185 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -global-isel=1 < %s | FileCheck %s
-
-; CHECK-NOT: movk
-
-define dso_local noundef i1 @ule_11111111(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ult i32 %0, 286331154
- ret i1 %2
-}
-
-define dso_local noundef i1 @ule_22222222(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ult i32 %0, 572662307
- ret i1 %2
-}
-
-define dso_local noundef i1 @ule_33333333(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ult i32 %0, 858993460
- ret i1 %2
-}
-
-define dso_local noundef i1 @ule_44444444(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ult i32 %0, 1145324613
- ret i1 %2
-}
-
-define dso_local noundef i1 @ule_55555555(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ult i32 %0, 1431655766
- ret i1 %2
-}
-
-define dso_local noundef i1 @ule_66666666(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ult i32 %0, 1717986919
- ret i1 %2
-}
-
-define dso_local noundef i1 @ule_77777777(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ult i32 %0, 2004318072
- ret i1 %2
-}
-
-define dso_local noundef i1 @ule_88888888(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ult i32 %0, -2004318071
- ret i1 %2
-}
-
-define dso_local noundef i1 @ule_99999999(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ult i32 %0, -1717986918
- ret i1 %2
-}
-
-define dso_local noundef i1 @uge_11111111(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ugt i32 %0, 286331152
- ret i1 %2
-}
-
-define dso_local noundef i1 @uge_22222222(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ugt i32 %0, 572662305
- ret i1 %2
-}
-
-define dso_local noundef i1 @uge_33333333(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ugt i32 %0, 858993458
- ret i1 %2
-}
-
-define dso_local noundef i1 @uge_44444444(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ugt i32 %0, 1145324611
- ret i1 %2
-}
-
-define dso_local noundef i1 @uge_55555555(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ugt i32 %0, 1431655764
- ret i1 %2
-}
-
-define dso_local noundef i1 @uge_66666666(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ugt i32 %0, 1717986917
- ret i1 %2
-}
-
-define dso_local noundef i1 @uge_77777777(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ugt i32 %0, 2004318070
- ret i1 %2
-}
-
-define dso_local noundef i1 @uge_88888888(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ugt i32 %0, -2004318073
- ret i1 %2
-}
-
-define dso_local noundef i1 @uge_99999999(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ugt i32 %0, -1717986920
- ret i1 %2
-}
-
-define dso_local noundef i1 @sle_11111111(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp slt i32 %0, 286331154
- ret i1 %2
-}
-
-define dso_local noundef i1 @sle_22222222(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp slt i32 %0, 572662307
- ret i1 %2
-}
-
-define dso_local noundef i1 @sle_33333333(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp slt i32 %0, 858993460
- ret i1 %2
-}
-
-define dso_local noundef i1 @sle_44444444(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp slt i32 %0, 1145324613
- ret i1 %2
-}
-
-define dso_local noundef i1 @sle_55555555(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp slt i32 %0, 1431655766
- ret i1 %2
-}
-
-define dso_local noundef i1 @sle_66666666(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp slt i32 %0, 1717986919
- ret i1 %2
-}
-
-define dso_local noundef i1 @sle_77777777(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp slt i32 %0, 2004318072
- ret i1 %2
-}
-
-define dso_local noundef i1 @sle_88888888(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ult i32 %0, -2004318071
- ret i1 %2
-}
-
-define dso_local noundef i1 @sle_99999999(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ult i32 %0, -1717986918
- ret i1 %2
-}
-
-define dso_local noundef i1 @sge_11111111(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp sgt i32 %0, 286331152
- ret i1 %2
-}
-
-define dso_local noundef i1 @sge_22222222(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp sgt i32 %0, 572662305
- ret i1 %2
-}
-
-define dso_local noundef i1 @sge_33333333(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp sgt i32 %0, 858993458
- ret i1 %2
-}
-
-define dso_local noundef i1 @sge_44444444(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp sgt i32 %0, 1145324611
- ret i1 %2
-}
-
-define dso_local noundef i1 @sge_55555555(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp sgt i32 %0, 1431655764
- ret i1 %2
-}
-
-define dso_local noundef i1 @sge_66666666(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp sgt i32 %0, 1717986917
- ret i1 %2
-}
-
-define dso_local noundef i1 @sge_77777777(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp sgt i32 %0, 2004318070
- ret i1 %2
-}
-
-define dso_local noundef i1 @sge_88888888(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ugt i32 %0, -2004318073
- ret i1 %2
-}
-
-define dso_local noundef i1 @sge_99999999(i32 noundef %0) local_unnamed_addr #0 {
- %2 = icmp ugt i32 %0, -1717986920
- ret i1 %2
-}
-
-attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a,-fmv" }
\ No newline at end of file
diff --git a/llvm/test/CodeGen/AArch64/icmp-cst.ll b/llvm/test/CodeGen/AArch64/icmp-cst.ll
new file mode 100644
index 00000000000000..e3768c1870c26a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/icmp-cst.ll
@@ -0,0 +1,687 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64-linux-gnu -global-isel=1 < %s | FileCheck --check-prefix=GISEL %s
+; RUN: llc -mtriple=aarch64-linux-gnu -global-isel=0 < %s | FileCheck --check-prefix=SDAG %s
+
+define i1 @ule_11111111(i32 noundef %0) {
+; GISEL-LABEL: ule_11111111:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #286331153 // =0x11111111
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ls
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: ule_11111111:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #4370 // =0x1112
+; SDAG-NEXT: movk w8, #4369, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lo
+; SDAG-NEXT: ret
+ %2 = icmp ult i32 %0, 286331154
+ ret i1 %2
+}
+
+define i1 @ule_22222222(i32 noundef %0) {
+; GISEL-LABEL: ule_22222222:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #572662306 // =0x22222222
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ls
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: ule_22222222:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #8739 // =0x2223
+; SDAG-NEXT: movk w8, #8738, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lo
+; SDAG-NEXT: ret
+ %2 = icmp ult i32 %0, 572662307
+ ret i1 %2
+}
+
+define i1 @ule_33333333(i32 noundef %0) {
+; GISEL-LABEL: ule_33333333:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #858993459 // =0x33333333
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ls
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: ule_33333333:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #13108 // =0x3334
+; SDAG-NEXT: movk w8, #13107, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lo
+; SDAG-NEXT: ret
+ %2 = icmp ult i32 %0, 858993460
+ ret i1 %2
+}
+
+define i1 @ule_44444444(i32 noundef %0) {
+; GISEL-LABEL: ule_44444444:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #1145324612 // =0x44444444
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ls
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: ule_44444444:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #17477 // =0x4445
+; SDAG-NEXT: movk w8, #17476, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lo
+; SDAG-NEXT: ret
+ %2 = icmp ult i32 %0, 1145324613
+ ret i1 %2
+}
+
+define i1 @ule_55555555(i32 noundef %0) {
+; GISEL-LABEL: ule_55555555:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #1431655765 // =0x55555555
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ls
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: ule_55555555:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #21846 // =0x5556
+; SDAG-NEXT: movk w8, #21845, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lo
+; SDAG-NEXT: ret
+ %2 = icmp ult i32 %0, 1431655766
+ ret i1 %2
+}
+
+define i1 @ule_66666666(i32 noundef %0) {
+; GISEL-LABEL: ule_66666666:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #1717986918 // =0x66666666
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ls
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: ule_66666666:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #26215 // =0x6667
+; SDAG-NEXT: movk w8, #26214, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lo
+; SDAG-NEXT: ret
+ %2 = icmp ult i32 %0, 1717986919
+ ret i1 %2
+}
+
+define i1 @ule_77777777(i32 noundef %0) {
+; GISEL-LABEL: ule_77777777:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #2004318071 // =0x77777777
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ls
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: ule_77777777:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #30584 // =0x7778
+; SDAG-NEXT: movk w8, #30583, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lo
+; SDAG-NEXT: ret
+ %2 = icmp ult i32 %0, 2004318072
+ ret i1 %2
+}
+
+define i1 @ule_88888888(i32 noundef %0) {
+; GISEL-LABEL: ule_88888888:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #-2004318072 // =0x88888888
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ls
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: ule_88888888:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #34953 // =0x8889
+; SDAG-NEXT: movk w8, #34952, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lo
+; SDAG-NEXT: ret
+ %2 = icmp ult i32 %0, -2004318071
+ ret i1 %2
+}
+
+define i1 @ule_99999999(i32 noundef %0) {
+; GISEL-LABEL: ule_99999999:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #-1717986919 // =0x99999999
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ls
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: ule_99999999:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #39322 // =0x999a
+; SDAG-NEXT: movk w8, #39321, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lo
+; SDAG-NEXT: ret
+ %2 = icmp ult i32 %0, -1717986918
+ ret i1 %2
+}
+
+define i1 @uge_11111111(i32 noundef %0) {
+; GISEL-LABEL: uge_11111111:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #286331153 // =0x11111111
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, hs
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: uge_11111111:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #4368 // =0x1110
+; SDAG-NEXT: movk w8, #4369, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, hi
+; SDAG-NEXT: ret
+ %2 = icmp ugt i32 %0, 286331152
+ ret i1 %2
+}
+
+define i1 @uge_22222222(i32 noundef %0) {
+; GISEL-LABEL: uge_22222222:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #572662306 // =0x22222222
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, hs
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: uge_22222222:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #8737 // =0x2221
+; SDAG-NEXT: movk w8, #8738, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, hi
+; SDAG-NEXT: ret
+ %2 = icmp ugt i32 %0, 572662305
+ ret i1 %2
+}
+
+define i1 @uge_33333333(i32 noundef %0) {
+; GISEL-LABEL: uge_33333333:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #858993459 // =0x33333333
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, hs
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: uge_33333333:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #13106 // =0x3332
+; SDAG-NEXT: movk w8, #13107, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, hi
+; SDAG-NEXT: ret
+ %2 = icmp ugt i32 %0, 858993458
+ ret i1 %2
+}
+
+define i1 @uge_44444444(i32 noundef %0) {
+; GISEL-LABEL: uge_44444444:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #1145324612 // =0x44444444
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, hs
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: uge_44444444:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #17475 // =0x4443
+; SDAG-NEXT: movk w8, #17476, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, hi
+; SDAG-NEXT: ret
+ %2 = icmp ugt i32 %0, 1145324611
+ ret i1 %2
+}
+
+define i1 @uge_55555555(i32 noundef %0) {
+; GISEL-LABEL: uge_55555555:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #1431655765 // =0x55555555
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, hs
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: uge_55555555:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #21844 // =0x5554
+; SDAG-NEXT: movk w8, #21845, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, hi
+; SDAG-NEXT: ret
+ %2 = icmp ugt i32 %0, 1431655764
+ ret i1 %2
+}
+
+define i1 @uge_66666666(i32 noundef %0) {
+; GISEL-LABEL: uge_66666666:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #1717986918 // =0x66666666
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, hs
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: uge_66666666:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #26213 // =0x6665
+; SDAG-NEXT: movk w8, #26214, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, hi
+; SDAG-NEXT: ret
+ %2 = icmp ugt i32 %0, 1717986917
+ ret i1 %2
+}
+
+define i1 @uge_77777777(i32 noundef %0) {
+; GISEL-LABEL: uge_77777777:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #2004318071 // =0x77777777
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, hs
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: uge_77777777:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #30582 // =0x7776
+; SDAG-NEXT: movk w8, #30583, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, hi
+; SDAG-NEXT: ret
+ %2 = icmp ugt i32 %0, 2004318070
+ ret i1 %2
+}
+
+define i1 @uge_88888888(i32 noundef %0) {
+; GISEL-LABEL: uge_88888888:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #-2004318072 // =0x88888888
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, hs
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: uge_88888888:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #34951 // =0x8887
+; SDAG-NEXT: movk w8, #34952, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, hi
+; SDAG-NEXT: ret
+ %2 = icmp ugt i32 %0, -2004318073
+ ret i1 %2
+}
+
+define i1 @uge_99999999(i32 noundef %0) {
+; GISEL-LABEL: uge_99999999:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #-1717986919 // =0x99999999
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, hs
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: uge_99999999:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #39320 // =0x9998
+; SDAG-NEXT: movk w8, #39321, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, hi
+; SDAG-NEXT: ret
+ %2 = icmp ugt i32 %0, -1717986920
+ ret i1 %2
+}
+
+define i1 @sle_11111111(i32 noundef %0) {
+; GISEL-LABEL: sle_11111111:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #286331153 // =0x11111111
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, le
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sle_11111111:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #4370 // =0x1112
+; SDAG-NEXT: movk w8, #4369, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lt
+; SDAG-NEXT: ret
+ %2 = icmp slt i32 %0, 286331154
+ ret i1 %2
+}
+
+define i1 @sle_22222222(i32 noundef %0) {
+; GISEL-LABEL: sle_22222222:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #572662306 // =0x22222222
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, le
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sle_22222222:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #8739 // =0x2223
+; SDAG-NEXT: movk w8, #8738, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lt
+; SDAG-NEXT: ret
+ %2 = icmp slt i32 %0, 572662307
+ ret i1 %2
+}
+
+define i1 @sle_33333333(i32 noundef %0) {
+; GISEL-LABEL: sle_33333333:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #858993459 // =0x33333333
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, le
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sle_33333333:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #13108 // =0x3334
+; SDAG-NEXT: movk w8, #13107, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lt
+; SDAG-NEXT: ret
+ %2 = icmp slt i32 %0, 858993460
+ ret i1 %2
+}
+
+define i1 @sle_44444444(i32 noundef %0) {
+; GISEL-LABEL: sle_44444444:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #1145324612 // =0x44444444
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, le
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sle_44444444:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #17477 // =0x4445
+; SDAG-NEXT: movk w8, #17476, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lt
+; SDAG-NEXT: ret
+ %2 = icmp slt i32 %0, 1145324613
+ ret i1 %2
+}
+
+define i1 @sle_55555555(i32 noundef %0) {
+; GISEL-LABEL: sle_55555555:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #1431655765 // =0x55555555
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, le
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sle_55555555:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #21846 // =0x5556
+; SDAG-NEXT: movk w8, #21845, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lt
+; SDAG-NEXT: ret
+ %2 = icmp slt i32 %0, 1431655766
+ ret i1 %2
+}
+
+define i1 @sle_66666666(i32 noundef %0) {
+; GISEL-LABEL: sle_66666666:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #1717986918 // =0x66666666
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, le
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sle_66666666:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #26215 // =0x6667
+; SDAG-NEXT: movk w8, #26214, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lt
+; SDAG-NEXT: ret
+ %2 = icmp slt i32 %0, 1717986919
+ ret i1 %2
+}
+
+define i1 @sle_77777777(i32 noundef %0) {
+; GISEL-LABEL: sle_77777777:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #2004318071 // =0x77777777
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, le
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sle_77777777:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #30584 // =0x7778
+; SDAG-NEXT: movk w8, #30583, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lt
+; SDAG-NEXT: ret
+ %2 = icmp slt i32 %0, 2004318072
+ ret i1 %2
+}
+
+define i1 @sle_88888888(i32 noundef %0) {
+; GISEL-LABEL: sle_88888888:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #-2004318072 // =0x88888888
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ls
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sle_88888888:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #34953 // =0x8889
+; SDAG-NEXT: movk w8, #34952, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lo
+; SDAG-NEXT: ret
+ %2 = icmp ult i32 %0, -2004318071
+ ret i1 %2
+}
+
+define i1 @sle_99999999(i32 noundef %0) {
+; GISEL-LABEL: sle_99999999:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #-1717986919 // =0x99999999
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ls
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sle_99999999:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #39322 // =0x999a
+; SDAG-NEXT: movk w8, #39321, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, lo
+; SDAG-NEXT: ret
+ %2 = icmp ult i32 %0, -1717986918
+ ret i1 %2
+}
+
+define i1 @sge_11111111(i32 noundef %0) {
+; GISEL-LABEL: sge_11111111:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #286331153 // =0x11111111
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ge
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sge_11111111:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #4368 // =0x1110
+; SDAG-NEXT: movk w8, #4369, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, gt
+; SDAG-NEXT: ret
+ %2 = icmp sgt i32 %0, 286331152
+ ret i1 %2
+}
+
+define i1 @sge_22222222(i32 noundef %0) {
+; GISEL-LABEL: sge_22222222:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #572662306 // =0x22222222
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ge
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sge_22222222:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #8737 // =0x2221
+; SDAG-NEXT: movk w8, #8738, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, gt
+; SDAG-NEXT: ret
+ %2 = icmp sgt i32 %0, 572662305
+ ret i1 %2
+}
+
+define i1 @sge_33333333(i32 noundef %0) {
+; GISEL-LABEL: sge_33333333:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #858993459 // =0x33333333
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ge
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sge_33333333:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #13106 // =0x3332
+; SDAG-NEXT: movk w8, #13107, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, gt
+; SDAG-NEXT: ret
+ %2 = icmp sgt i32 %0, 858993458
+ ret i1 %2
+}
+
+define i1 @sge_44444444(i32 noundef %0) {
+; GISEL-LABEL: sge_44444444:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #1145324612 // =0x44444444
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ge
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sge_44444444:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #17475 // =0x4443
+; SDAG-NEXT: movk w8, #17476, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, gt
+; SDAG-NEXT: ret
+ %2 = icmp sgt i32 %0, 1145324611
+ ret i1 %2
+}
+
+define i1 @sge_55555555(i32 noundef %0) {
+; GISEL-LABEL: sge_55555555:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #1431655765 // =0x55555555
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ge
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sge_55555555:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #21844 // =0x5554
+; SDAG-NEXT: movk w8, #21845, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, gt
+; SDAG-NEXT: ret
+ %2 = icmp sgt i32 %0, 1431655764
+ ret i1 %2
+}
+
+define i1 @sge_66666666(i32 noundef %0) {
+; GISEL-LABEL: sge_66666666:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #1717986918 // =0x66666666
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ge
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sge_66666666:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #26213 // =0x6665
+; SDAG-NEXT: movk w8, #26214, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, gt
+; SDAG-NEXT: ret
+ %2 = icmp sgt i32 %0, 1717986917
+ ret i1 %2
+}
+
+define i1 @sge_77777777(i32 noundef %0) {
+; GISEL-LABEL: sge_77777777:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #2004318071 // =0x77777777
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, ge
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sge_77777777:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #30582 // =0x7776
+; SDAG-NEXT: movk w8, #30583, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, gt
+; SDAG-NEXT: ret
+ %2 = icmp sgt i32 %0, 2004318070
+ ret i1 %2
+}
+
+define i1 @sge_88888888(i32 noundef %0) {
+; GISEL-LABEL: sge_88888888:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #-2004318072 // =0x88888888
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, hs
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sge_88888888:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #34951 // =0x8887
+; SDAG-NEXT: movk w8, #34952, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, hi
+; SDAG-NEXT: ret
+ %2 = icmp ugt i32 %0, -2004318073
+ ret i1 %2
+}
+
+define i1 @sge_99999999(i32 noundef %0) {
+; GISEL-LABEL: sge_99999999:
+; GISEL: // %bb.0:
+; GISEL-NEXT: mov w8, #-1717986919 // =0x99999999
+; GISEL-NEXT: cmp w0, w8
+; GISEL-NEXT: cset w0, hs
+; GISEL-NEXT: ret
+;
+; SDAG-LABEL: sge_99999999:
+; SDAG: // %bb.0:
+; SDAG-NEXT: mov w8, #39320 // =0x9998
+; SDAG-NEXT: movk w8, #39321, lsl #16
+; SDAG-NEXT: cmp w0, w8
+; SDAG-NEXT: cset w0, hi
+; SDAG-NEXT: ret
+ %2 = icmp ugt i32 %0, -1717986920
+ ret i1 %2
+}
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