[llvm] [RISCV] Prefer whole register loads and stores when VL=VLMAX (PR #75531)

[Luke Lau via llvm-commits]

================
@@ -9882,12 +9895,22 @@ RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op,
 
   MVT ContainerVT = getContainerForFixedLengthVector(VT);
 
-  SDValue VL = getVLOp(VT.getVectorNumElements(), ContainerVT, DL, DAG,
-                       Subtarget);
-
   SDValue NewValue =
       convertToScalableVector(ContainerVT, StoreVal, DAG, Subtarget);
 
+
+  // If we know the exact VLEN and our fixed length vector completely fills
+  // the container, use a whole register store instead.
+  const auto [MinVLMAX, MaxVLMAX] =
+      RISCVTargetLowering::computeVLMAXBounds(ContainerVT, Subtarget);
+  if (MinVLMAX == MaxVLMAX && MinVLMAX == VT.getVectorNumElements() &&
+      getLMUL1VT(ContainerVT).bitsLE(ContainerVT))
+    return DAG.getStore(Store->getChain(), DL, NewValue, Store->getBasePtr(),
+                        Store->getMemOperand());
----------------
lukel97 wrote:

Looks like it isn't affected by the actual use of vs1r.v itself, since replacing the patterns to emit vse64.vs still miscompiles.

The resulting diff shows that some of these stores are reordered, and the memory VT of the node also changes from `v2i64` to `nxv1i64`. I'm not sure if these are related.

https://github.com/llvm/llvm-project/pull/75531