[llvm] [RISCV] Move V0 to the end of register allocation order (PR #82967)

[Philip Reames via llvm-commits]

================
@@ -510,17 +510,17 @@ defvar VM8VTs = [vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t,
 
 def VR : VReg<!listconcat(VM1VTs, VMaskVTs),
               (add (sequence "V%u", 8, 31),
-                   (sequence "V%u", 0, 7)), 1>;
+                   (sequence "V%u", 1, 7), V0), 1>;
----------------
preames wrote:

Our order here should probably account for LMUL groups.  With the suggested order here, we kill two m2 register groups as soon as we allocate v1, v2.  If we did these in the reverse order, and allocated v7 then v6, we'd only kill one.  Previously, the order didn't matter, but with moving v0 to the end I think it does.  

https://github.com/llvm/llvm-project/pull/82967