[llvm] [AMDGPU][AsmParser] Support structured HWREG operands. (PR #82805)

[Jay Foad via llvm-commits]

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@@ -7730,6 +7741,44 @@ AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const {
   return getOperandLoc(Test, Operands);
 }
 
+ParseStatus
+AMDGPUAsmParser::parseStructuredOpFields(ArrayRef<StructuredOpField *> Fields) {
+  if (!trySkipToken(AsmToken::LCurly))
+    return ParseStatus::NoMatch;
+
+  bool First = true;
+  while (!trySkipToken(AsmToken::RCurly)) {
+    if (!First && !skipToken(AsmToken::Comma, "comma expected"))
+      return ParseStatus::Failure;
+
+    StringRef Id = getTokenStr();
+    SMLoc IdLoc = getLoc();
+    if (!skipToken(AsmToken::Identifier, "field name expected") ||
+        !skipToken(AsmToken::Colon, "colon expected"))
+      return ParseStatus::Failure;
+
+    auto I =
+        find_if(Fields, [Id](StructuredOpField *F) { return F->Id == Id; });
+    if (I == Fields.end())
+      return Error(IdLoc, "unknown field");
+
+    // TODO: Support symbolic values.
----------------
jayfoad wrote:

Diagnose duplicate fields here, like `{id:1,id:2}`? What does SP3 do?

https://github.com/llvm/llvm-project/pull/82805