[llvm] [llvm][arm] add T1 and T2 assembly options for vlldm and vlstm (PR #83116)

[via llvm-commits]

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@@ -8731,6 +8768,34 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
   }
 
   switch (Inst.getOpcode()) {
+  case ARM::VLLDM:
+    [[fallthrough]];
+  case ARM::VLSTM: {
+    // In some cases both T1 and T2 are valid, causing tablegen pick T1 instead
+    // of T2
+    if (Operands.size() == 4) { // a register list has been provided
+      ARMOperand &Op = static_cast<ARMOperand &>(
+          *Operands[3]); // the register list, a dpr_reglist
+      if (Op.isDPRRegList()) {
+        auto &RegList = Op.getRegList();
+        // When the register list is {d0-d31} the instruction has to be the T2
+        // variant
+        if (RegList.size() == 32) {
+          const unsigned Opcode =
+              (Inst.getOpcode() == ARM::VLLDM) ? ARM::VLLDM_T2 : ARM::VLSTM_T2;
+          MCInst TmpInst;
+          TmpInst.setOpcode(Opcode);
+          TmpInst.addOperand(Inst.getOperand(0));
+          TmpInst.addOperand(Inst.getOperand(1));
+          TmpInst.addOperand(Inst.getOperand(2));
+          TmpInst.addOperand(Inst.getOperand(3));
+          Inst = TmpInst;
+          return true;
+        }
+      }
+    }
+    return false;
+  }
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sivan-shani wrote:

Essentially yes, TableGen can not distinguish between `DPRRegList` of 16/32 registers.
As a default, it picks the 16 regs case (T1)

https://github.com/llvm/llvm-project/pull/83116