[llvm] [llvm][arm] add T1 and T2 assembly options for vlldm and vlstm (PR #83116)

[via llvm-commits]

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@@ -7596,6 +7601,38 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
 
   const unsigned Opcode = Inst.getOpcode();
   switch (Opcode) {
+  case ARM::VLLDM:
+    [[fallthrough]];
+  case ARM::VLLDM_T2:
+    [[fallthrough]];
+  case ARM::VLSTM:
+    [[fallthrough]];
+  case ARM::VLSTM_T2: {
+    // Since in some cases both T1 and T2 are valid, tablegen can not always
+    // pick the correct instruction.
+    if (Operands.size() == 4) { // a register list has been provided
+      ARMOperand &Op = static_cast<ARMOperand &>(
+          *Operands[3]); // the register list, a dpr_reglist
+      if (Op.isDPRRegList()) {
+        auto &RegList = Op.getRegList();
+        // T2 requires v8.1-M.Main (cannot be handled by tablegen)
+        if (RegList.size() == 32 && !hasV8_1MMainline()) {
+          return Error(Op.getEndLoc(), "T2 version requires v8.1-M.Main");
+        }
+        // When target has 32 D registers, T1 is undefined.
+        if (hasD32() && RegList.size() != 32) {
+          return Error(Op.getEndLoc(), "operand must be exactly {d0-d31}");
+        }
+        // When target has 16 D registers, both T1 and T2 are valid.
----------------
sivan-shani wrote:

>From the Arm ARM pseudo code it seems that T2 might work also when target has 16 D regs.
The only explicit NOP cases are when:
1. Secure Floating-point is not in use.
2. Floating-point Extension and MVE are not implemented.

https://github.com/llvm/llvm-project/pull/83116