[llvm] [AArch64][GlobalISel] Basic add_sat and sub_sat vector handling. (PR #80650)

[David Green via llvm-commits]

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@@ -1153,8 +1150,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .minScalarEltSameAsIf(always, 1, 0)
       .maxScalarEltSameAsIf(always, 1, 0);
 
-  // TODO: Vector types.
-  getActionDefinitionsBuilder({G_SADDSAT, G_SSUBSAT}).lowerIf(isScalar(0));
+  getActionDefinitionsBuilder({G_UADDSAT, G_SADDSAT, G_USUBSAT, G_SSUBSAT})
+      .legalFor({v2s64, v2s32, v4s32, v4s16, v8s16, v8s8, v16s8})
+      .clampNumElements(0, v8s8, v16s8)
+      .clampNumElements(0, v4s16, v8s16)
+      .clampNumElements(0, v2s32, v4s32)
+      .clampMaxNumElements(0, s64, 2)
+      .moreElementsToNextPow2(0)
+      .lowerIf(isScalar(0));
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davemgreen wrote:

Yeah - it is a 'else' instead of 'unreachable'. I would just personally prefer that this failed during legalization (and fell back to SDAG) than it being untested, or tried to handle every different case in a single patch. I can change it to a lower though, we should get test coverage when the other operations are able to handle non-power-2 vector sizes.

https://github.com/llvm/llvm-project/pull/80650