[llvm] 28c29fb - [RISCV] Add exact VLEN RUNs for insert_subvector and concat_vector tests. NFC
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 27 22:45:28 PST 2024
Author: Luke Lau
Date: 2024-02-28T14:44:42+08:00
New Revision: 28c29fbec3057692a7985819d799a9e5d47eb2d1
URL: https://github.com/llvm/llvm-project/commit/28c29fbec3057692a7985819d799a9e5d47eb2d1
DIFF: https://github.com/llvm/llvm-project/commit/28c29fbec3057692a7985819d799a9e5d47eb2d1.diff
LOG: [RISCV] Add exact VLEN RUNs for insert_subvector and concat_vector tests. NFC
Also update the RUNs in the extract_subvector tests to be consistent.
Using the term VLS/VLA here as it's more succinct than KNOWNVLEN/UNKNOWNVLEN.
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
index c49b1a7ad1861d..b9c611bf3e54a8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
@@ -1,6 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v -riscv-v-vector-bits-max=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-KNOWNVLEN128
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
+
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
+
+; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS %s
define void @extract_v2i8_v4i8_0(ptr %x, ptr %y) {
; CHECK-LABEL: extract_v2i8_v4i8_0:
@@ -63,22 +69,22 @@ define void @extract_v2i8_v8i8_6(ptr %x, ptr %y) {
}
define void @extract_v1i32_v8i32_4(ptr %x, ptr %y) {
-; CHECK-V-LABEL: extract_v1i32_v8i32_4:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-V-NEXT: vle32.v v8, (a0)
-; CHECK-V-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; CHECK-V-NEXT: vslidedown.vi v8, v8, 4
-; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-V-NEXT: vse32.v v8, (a1)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v1i32_v8i32_4:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vle32.v v8, (a0)
+; VLA-NEXT: vsetivli zero, 1, e32, m2, ta, ma
+; VLA-NEXT: vslidedown.vi v8, v8, 4
+; VLA-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; VLA-NEXT: vse32.v v8, (a1)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v1i32_v8i32_4:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vl2re32.v v8, (a0)
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vse32.v v9, (a1)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v1i32_v8i32_4:
+; VLS: # %bb.0:
+; VLS-NEXT: vl2re32.v v8, (a0)
+; VLS-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; VLS-NEXT: vse32.v v9, (a1)
+; VLS-NEXT: ret
%a = load <8 x i32>, ptr %x
%c = call <1 x i32> @llvm.vector.extract.v1i32.v8i32(<8 x i32> %a, i64 4)
store <1 x i32> %c, ptr %y
@@ -86,24 +92,24 @@ define void @extract_v1i32_v8i32_4(ptr %x, ptr %y) {
}
define void @extract_v1i32_v8i32_5(ptr %x, ptr %y) {
-; CHECK-V-LABEL: extract_v1i32_v8i32_5:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-V-NEXT: vle32.v v8, (a0)
-; CHECK-V-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; CHECK-V-NEXT: vslidedown.vi v8, v8, 5
-; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-V-NEXT: vse32.v v8, (a1)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v1i32_v8i32_5:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vle32.v v8, (a0)
+; VLA-NEXT: vsetivli zero, 1, e32, m2, ta, ma
+; VLA-NEXT: vslidedown.vi v8, v8, 5
+; VLA-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; VLA-NEXT: vse32.v v8, (a1)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v1i32_v8i32_5:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vl2re32.v v8, (a0)
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vse32.v v8, (a1)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v1i32_v8i32_5:
+; VLS: # %bb.0:
+; VLS-NEXT: vl2re32.v v8, (a0)
+; VLS-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; VLS-NEXT: vslidedown.vi v8, v9, 1
+; VLS-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; VLS-NEXT: vse32.v v8, (a1)
+; VLS-NEXT: ret
%a = load <8 x i32>, ptr %x
%c = call <1 x i32> @llvm.vector.extract.v1i32.v8i32(<8 x i32> %a, i64 5)
store <1 x i32> %c, ptr %y
@@ -111,20 +117,20 @@ define void @extract_v1i32_v8i32_5(ptr %x, ptr %y) {
}
define void @extract_v2i32_v8i32_0(ptr %x, ptr %y) {
-; CHECK-V-LABEL: extract_v2i32_v8i32_0:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-V-NEXT: vle32.v v8, (a0)
-; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-V-NEXT: vse32.v v8, (a1)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v2i32_v8i32_0:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vle32.v v8, (a0)
+; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLA-NEXT: vse32.v v8, (a1)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v2i32_v8i32_0:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vl2re32.v v8, (a0)
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vse32.v v8, (a1)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v2i32_v8i32_0:
+; VLS: # %bb.0:
+; VLS-NEXT: vl2re32.v v8, (a0)
+; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLS-NEXT: vse32.v v8, (a1)
+; VLS-NEXT: ret
%a = load <8 x i32>, ptr %x
%c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 0)
store <2 x i32> %c, ptr %y
@@ -132,24 +138,24 @@ define void @extract_v2i32_v8i32_0(ptr %x, ptr %y) {
}
define void @extract_v2i32_v8i32_2(ptr %x, ptr %y) {
-; CHECK-V-LABEL: extract_v2i32_v8i32_2:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-V-NEXT: vle32.v v8, (a0)
-; CHECK-V-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-V-NEXT: vslidedown.vi v8, v8, 2
-; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-V-NEXT: vse32.v v8, (a1)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v2i32_v8i32_2:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vle32.v v8, (a0)
+; VLA-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; VLA-NEXT: vslidedown.vi v8, v8, 2
+; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLA-NEXT: vse32.v v8, (a1)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v2i32_v8i32_2:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vl2re32.v v8, (a0)
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v8, 2
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vse32.v v8, (a1)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v2i32_v8i32_2:
+; VLS: # %bb.0:
+; VLS-NEXT: vl2re32.v v8, (a0)
+; VLS-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; VLS-NEXT: vslidedown.vi v8, v8, 2
+; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLS-NEXT: vse32.v v8, (a1)
+; VLS-NEXT: ret
%a = load <8 x i32>, ptr %x
%c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 2)
store <2 x i32> %c, ptr %y
@@ -157,22 +163,22 @@ define void @extract_v2i32_v8i32_2(ptr %x, ptr %y) {
}
define void @extract_v2i32_v8i32_4(ptr %x, ptr %y) {
-; CHECK-V-LABEL: extract_v2i32_v8i32_4:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-V-NEXT: vle32.v v8, (a0)
-; CHECK-V-NEXT: vsetivli zero, 2, e32, m2, ta, ma
-; CHECK-V-NEXT: vslidedown.vi v8, v8, 4
-; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-V-NEXT: vse32.v v8, (a1)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v2i32_v8i32_4:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vle32.v v8, (a0)
+; VLA-NEXT: vsetivli zero, 2, e32, m2, ta, ma
+; VLA-NEXT: vslidedown.vi v8, v8, 4
+; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLA-NEXT: vse32.v v8, (a1)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v2i32_v8i32_4:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vl2re32.v v8, (a0)
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vse32.v v9, (a1)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v2i32_v8i32_4:
+; VLS: # %bb.0:
+; VLS-NEXT: vl2re32.v v8, (a0)
+; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLS-NEXT: vse32.v v9, (a1)
+; VLS-NEXT: ret
%a = load <8 x i32>, ptr %x
%c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 4)
store <2 x i32> %c, ptr %y
@@ -180,24 +186,24 @@ define void @extract_v2i32_v8i32_4(ptr %x, ptr %y) {
}
define void @extract_v2i32_v8i32_6(ptr %x, ptr %y) {
-; CHECK-V-LABEL: extract_v2i32_v8i32_6:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-V-NEXT: vle32.v v8, (a0)
-; CHECK-V-NEXT: vsetivli zero, 2, e32, m2, ta, ma
-; CHECK-V-NEXT: vslidedown.vi v8, v8, 6
-; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-V-NEXT: vse32.v v8, (a1)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v2i32_v8i32_6:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vle32.v v8, (a0)
+; VLA-NEXT: vsetivli zero, 2, e32, m2, ta, ma
+; VLA-NEXT: vslidedown.vi v8, v8, 6
+; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLA-NEXT: vse32.v v8, (a1)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v2i32_v8i32_6:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vl2re32.v v8, (a0)
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v9, 2
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vse32.v v8, (a1)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v2i32_v8i32_6:
+; VLS: # %bb.0:
+; VLS-NEXT: vl2re32.v v8, (a0)
+; VLS-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; VLS-NEXT: vslidedown.vi v8, v9, 2
+; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLS-NEXT: vse32.v v8, (a1)
+; VLS-NEXT: ret
%a = load <8 x i32>, ptr %x
%c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 6)
store <2 x i32> %c, ptr %y
@@ -230,59 +236,59 @@ define void @extract_v2i32_nxv16i32_2(<vscale x 16 x i32> %x, ptr %y) {
}
define void @extract_v2i32_nxv16i32_4(<vscale x 16 x i32> %x, ptr %y) {
-; CHECK-V-LABEL: extract_v2i32_nxv16i32_4:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: vsetivli zero, 2, e32, m2, ta, ma
-; CHECK-V-NEXT: vslidedown.vi v8, v8, 4
-; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-V-NEXT: vse32.v v8, (a0)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v2i32_nxv16i32_4:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 2, e32, m2, ta, ma
+; VLA-NEXT: vslidedown.vi v8, v8, 4
+; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLA-NEXT: vse32.v v8, (a0)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v2i32_nxv16i32_4:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vse32.v v9, (a0)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v2i32_nxv16i32_4:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLS-NEXT: vse32.v v9, (a0)
+; VLS-NEXT: ret
%c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 4)
store <2 x i32> %c, ptr %y
ret void
}
define void @extract_v2i32_nxv16i32_6(<vscale x 16 x i32> %x, ptr %y) {
-; CHECK-V-LABEL: extract_v2i32_nxv16i32_6:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: vsetivli zero, 2, e32, m2, ta, ma
-; CHECK-V-NEXT: vslidedown.vi v8, v8, 6
-; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-V-NEXT: vse32.v v8, (a0)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v2i32_nxv16i32_6:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 2, e32, m2, ta, ma
+; VLA-NEXT: vslidedown.vi v8, v8, 6
+; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLA-NEXT: vse32.v v8, (a0)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v2i32_nxv16i32_6:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v9, 2
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vse32.v v8, (a0)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v2i32_nxv16i32_6:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; VLS-NEXT: vslidedown.vi v8, v9, 2
+; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLS-NEXT: vse32.v v8, (a0)
+; VLS-NEXT: ret
%c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 6)
store <2 x i32> %c, ptr %y
ret void
}
define void @extract_v2i32_nxv16i32_8(<vscale x 16 x i32> %x, ptr %y) {
-; CHECK-V-LABEL: extract_v2i32_nxv16i32_8:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: vsetivli zero, 2, e32, m4, ta, ma
-; CHECK-V-NEXT: vslidedown.vi v8, v8, 8
-; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-V-NEXT: vse32.v v8, (a0)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v2i32_nxv16i32_8:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 2, e32, m4, ta, ma
+; VLA-NEXT: vslidedown.vi v8, v8, 8
+; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLA-NEXT: vse32.v v8, (a0)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v2i32_nxv16i32_8:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vse32.v v10, (a0)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v2i32_nxv16i32_8:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLS-NEXT: vse32.v v10, (a0)
+; VLS-NEXT: ret
%c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 8)
store <2 x i32> %c, ptr %y
ret void
@@ -339,40 +345,40 @@ define void @extract_v2i8_nxv2i8_6(<vscale x 2 x i8> %x, ptr %y) {
}
define void @extract_v8i32_nxv16i32_8(<vscale x 16 x i32> %x, ptr %y) {
-; CHECK-V-LABEL: extract_v8i32_nxv16i32_8:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: vsetivli zero, 8, e32, m4, ta, ma
-; CHECK-V-NEXT: vslidedown.vi v8, v8, 8
-; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-V-NEXT: vse32.v v8, (a0)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v8i32_nxv16i32_8:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; VLA-NEXT: vslidedown.vi v8, v8, 8
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vse32.v v8, (a0)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v8i32_nxv16i32_8:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vs2r.v v10, (a0)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v8i32_nxv16i32_8:
+; VLS: # %bb.0:
+; VLS-NEXT: vs2r.v v10, (a0)
+; VLS-NEXT: ret
%c = call <8 x i32> @llvm.vector.extract.v8i32.nxv16i32(<vscale x 16 x i32> %x, i64 8)
store <8 x i32> %c, ptr %y
ret void
}
define void @extract_v8i1_v64i1_0(ptr %x, ptr %y) {
-; CHECK-V-LABEL: extract_v8i1_v64i1_0:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: li a2, 64
-; CHECK-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
-; CHECK-V-NEXT: vlm.v v8, (a0)
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vsm.v v8, (a1)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v8i1_v64i1_0:
+; VLA: # %bb.0:
+; VLA-NEXT: li a2, 64
+; VLA-NEXT: vsetvli zero, a2, e8, m4, ta, ma
+; VLA-NEXT: vlm.v v8, (a0)
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vsm.v v8, (a1)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v8i1_v64i1_0:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vsetvli a2, zero, e8, m4, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vlm.v v8, (a0)
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a1)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v8i1_v64i1_0:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetvli a2, zero, e8, m4, ta, ma
+; VLS-NEXT: vlm.v v8, (a0)
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vsm.v v8, (a1)
+; VLS-NEXT: ret
%a = load <64 x i1>, ptr %x
%c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 0)
store <8 x i1> %c, ptr %y
@@ -380,26 +386,26 @@ define void @extract_v8i1_v64i1_0(ptr %x, ptr %y) {
}
define void @extract_v8i1_v64i1_8(ptr %x, ptr %y) {
-; CHECK-V-LABEL: extract_v8i1_v64i1_8:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: li a2, 64
-; CHECK-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
-; CHECK-V-NEXT: vlm.v v8, (a0)
-; CHECK-V-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
-; CHECK-V-NEXT: vslidedown.vi v8, v8, 1
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vsm.v v8, (a1)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v8i1_v64i1_8:
+; VLA: # %bb.0:
+; VLA-NEXT: li a2, 64
+; VLA-NEXT: vsetvli zero, a2, e8, m4, ta, ma
+; VLA-NEXT: vlm.v v8, (a0)
+; VLA-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
+; VLA-NEXT: vslidedown.vi v8, v8, 1
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vsm.v v8, (a1)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v8i1_v64i1_8:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vsetvli a2, zero, e8, m4, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vlm.v v8, (a0)
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v8, 1
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a1)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v8i1_v64i1_8:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetvli a2, zero, e8, m4, ta, ma
+; VLS-NEXT: vlm.v v8, (a0)
+; VLS-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
+; VLS-NEXT: vslidedown.vi v8, v8, 1
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vsm.v v8, (a1)
+; VLS-NEXT: ret
%a = load <64 x i1>, ptr %x
%c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 8)
store <8 x i1> %c, ptr %y
@@ -407,26 +413,26 @@ define void @extract_v8i1_v64i1_8(ptr %x, ptr %y) {
}
define void @extract_v8i1_v64i1_48(ptr %x, ptr %y) {
-; CHECK-V-LABEL: extract_v8i1_v64i1_48:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: li a2, 64
-; CHECK-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
-; CHECK-V-NEXT: vlm.v v8, (a0)
-; CHECK-V-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
-; CHECK-V-NEXT: vslidedown.vi v8, v8, 6
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vsm.v v8, (a1)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v8i1_v64i1_48:
+; VLA: # %bb.0:
+; VLA-NEXT: li a2, 64
+; VLA-NEXT: vsetvli zero, a2, e8, m4, ta, ma
+; VLA-NEXT: vlm.v v8, (a0)
+; VLA-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
+; VLA-NEXT: vslidedown.vi v8, v8, 6
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vsm.v v8, (a1)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v8i1_v64i1_48:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vsetvli a2, zero, e8, m4, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vlm.v v8, (a0)
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v8, 6
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a1)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v8i1_v64i1_48:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetvli a2, zero, e8, m4, ta, ma
+; VLS-NEXT: vlm.v v8, (a0)
+; VLS-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
+; VLS-NEXT: vslidedown.vi v8, v8, 6
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vsm.v v8, (a1)
+; VLS-NEXT: ret
%a = load <64 x i1>, ptr %x
%c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 48)
store <8 x i1> %c, ptr %y
@@ -508,38 +514,38 @@ define void @extract_v8i1_nxv64i1_192(<vscale x 64 x i1> %x, ptr %y) {
}
define void @extract_v2i1_v64i1_0(ptr %x, ptr %y) {
-; CHECK-V-LABEL: extract_v2i1_v64i1_0:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: li a2, 64
-; CHECK-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
-; CHECK-V-NEXT: vlm.v v0, (a0)
-; CHECK-V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-V-NEXT: vmv.v.i v8, 0
-; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vmv.v.i v9, 0
-; CHECK-V-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-V-NEXT: vmv.v.v v9, v8
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vmsne.vi v8, v9, 0
-; CHECK-V-NEXT: vsm.v v8, (a1)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v2i1_v64i1_0:
+; VLA: # %bb.0:
+; VLA-NEXT: li a2, 64
+; VLA-NEXT: vsetvli zero, a2, e8, m4, ta, ma
+; VLA-NEXT: vlm.v v0, (a0)
+; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLA-NEXT: vmv.v.i v8, 0
+; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vmv.v.i v9, 0
+; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; VLA-NEXT: vmv.v.v v9, v8
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vmsne.vi v8, v9, 0
+; VLA-NEXT: vsm.v v8, (a1)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v2i1_v64i1_0:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vsetvli a2, zero, e8, m4, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vlm.v v0, (a0)
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v9, 0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.v v9, v8
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v8, v9, 0
-; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a1)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v2i1_v64i1_0:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetvli a2, zero, e8, m4, ta, ma
+; VLS-NEXT: vlm.v v0, (a0)
+; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vmv.v.i v9, 0
+; VLS-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; VLS-NEXT: vmv.v.v v9, v8
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vmsne.vi v8, v9, 0
+; VLS-NEXT: vsm.v v8, (a1)
+; VLS-NEXT: ret
%a = load <64 x i1>, ptr %x
%c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0)
store <2 x i1> %c, ptr %y
@@ -547,48 +553,48 @@ define void @extract_v2i1_v64i1_0(ptr %x, ptr %y) {
}
define void @extract_v2i1_v64i1_2(ptr %x, ptr %y) {
-; CHECK-V-LABEL: extract_v2i1_v64i1_2:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: li a2, 64
-; CHECK-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
-; CHECK-V-NEXT: vlm.v v0, (a0)
-; CHECK-V-NEXT: vmv.v.i v8, 0
-; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-V-NEXT: vsetivli zero, 2, e8, m1, ta, ma
-; CHECK-V-NEXT: vslidedown.vi v8, v8, 2
-; CHECK-V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-V-NEXT: vmsne.vi v0, v8, 0
-; CHECK-V-NEXT: vmv.v.i v8, 0
-; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vmv.v.i v9, 0
-; CHECK-V-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-V-NEXT: vmv.v.v v9, v8
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vmsne.vi v8, v9, 0
-; CHECK-V-NEXT: vsm.v v8, (a1)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v2i1_v64i1_2:
+; VLA: # %bb.0:
+; VLA-NEXT: li a2, 64
+; VLA-NEXT: vsetvli zero, a2, e8, m4, ta, ma
+; VLA-NEXT: vlm.v v0, (a0)
+; VLA-NEXT: vmv.v.i v8, 0
+; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vsetivli zero, 2, e8, m1, ta, ma
+; VLA-NEXT: vslidedown.vi v8, v8, 2
+; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLA-NEXT: vmsne.vi v0, v8, 0
+; VLA-NEXT: vmv.v.i v8, 0
+; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vmv.v.i v9, 0
+; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; VLA-NEXT: vmv.v.v v9, v8
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vmsne.vi v8, v9, 0
+; VLA-NEXT: vsm.v v8, (a1)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v2i1_v64i1_2:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vsetvli a2, zero, e8, m4, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vlm.v v0, (a0)
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, m1, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v8, 2
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v0, v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v9, 0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.v v9, v8
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v8, v9, 0
-; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a1)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v2i1_v64i1_2:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetvli a2, zero, e8, m4, ta, ma
+; VLS-NEXT: vlm.v v0, (a0)
+; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma
+; VLS-NEXT: vslidedown.vi v8, v8, 2
+; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLS-NEXT: vmsne.vi v0, v8, 0
+; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vmv.v.i v9, 0
+; VLS-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; VLS-NEXT: vmv.v.v v9, v8
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vmsne.vi v8, v9, 0
+; VLS-NEXT: vsm.v v8, (a1)
+; VLS-NEXT: ret
%a = load <64 x i1>, ptr %x
%c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2)
store <2 x i1> %c, ptr %y
@@ -596,49 +602,49 @@ define void @extract_v2i1_v64i1_2(ptr %x, ptr %y) {
}
define void @extract_v2i1_v64i1_42(ptr %x, ptr %y) {
-; CHECK-V-LABEL: extract_v2i1_v64i1_42:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: li a2, 64
-; CHECK-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
-; CHECK-V-NEXT: vlm.v v0, (a0)
-; CHECK-V-NEXT: vmv.v.i v8, 0
-; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-V-NEXT: li a0, 42
-; CHECK-V-NEXT: vsetivli zero, 2, e8, m4, ta, ma
-; CHECK-V-NEXT: vslidedown.vx v8, v8, a0
-; CHECK-V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-V-NEXT: vmsne.vi v0, v8, 0
-; CHECK-V-NEXT: vmv.v.i v8, 0
-; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vmv.v.i v9, 0
-; CHECK-V-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-V-NEXT: vmv.v.v v9, v8
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vmsne.vi v8, v9, 0
-; CHECK-V-NEXT: vsm.v v8, (a1)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v2i1_v64i1_42:
+; VLA: # %bb.0:
+; VLA-NEXT: li a2, 64
+; VLA-NEXT: vsetvli zero, a2, e8, m4, ta, ma
+; VLA-NEXT: vlm.v v0, (a0)
+; VLA-NEXT: vmv.v.i v8, 0
+; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: li a0, 42
+; VLA-NEXT: vsetivli zero, 2, e8, m4, ta, ma
+; VLA-NEXT: vslidedown.vx v8, v8, a0
+; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLA-NEXT: vmsne.vi v0, v8, 0
+; VLA-NEXT: vmv.v.i v8, 0
+; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vmv.v.i v9, 0
+; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; VLA-NEXT: vmv.v.v v9, v8
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vmsne.vi v8, v9, 0
+; VLA-NEXT: vsm.v v8, (a1)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v2i1_v64i1_42:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vsetvli a2, zero, e8, m4, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vlm.v v0, (a0)
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, m1, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v10, 10
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v0, v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v9, 0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.v v9, v8
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v8, v9, 0
-; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a1)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v2i1_v64i1_42:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetvli a2, zero, e8, m4, ta, ma
+; VLS-NEXT: vlm.v v0, (a0)
+; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma
+; VLS-NEXT: vslidedown.vi v8, v10, 10
+; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLS-NEXT: vmsne.vi v0, v8, 0
+; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vmv.v.i v9, 0
+; VLS-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; VLS-NEXT: vmv.v.v v9, v8
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vmsne.vi v8, v9, 0
+; VLS-NEXT: vsm.v v8, (a1)
+; VLS-NEXT: ret
%a = load <64 x i1>, ptr %x
%c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42)
store <2 x i1> %c, ptr %y
@@ -665,45 +671,45 @@ define void @extract_v2i1_nxv2i1_0(<vscale x 2 x i1> %x, ptr %y) {
}
define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, ptr %y) {
-; CHECK-V-LABEL: extract_v2i1_nxv2i1_2:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-V-NEXT: vmv.v.i v8, 0
-; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-V-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-V-NEXT: vslidedown.vi v8, v8, 2
-; CHECK-V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-V-NEXT: vmsne.vi v0, v8, 0
-; CHECK-V-NEXT: vmv.v.i v8, 0
-; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vmv.v.i v9, 0
-; CHECK-V-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-V-NEXT: vmv.v.v v9, v8
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vmsne.vi v8, v9, 0
-; CHECK-V-NEXT: vsm.v v8, (a0)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v2i1_nxv2i1_2:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; VLA-NEXT: vmv.v.i v8, 0
+; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; VLA-NEXT: vslidedown.vi v8, v8, 2
+; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLA-NEXT: vmsne.vi v0, v8, 0
+; VLA-NEXT: vmv.v.i v8, 0
+; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vmv.v.i v9, 0
+; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; VLA-NEXT: vmv.v.v v9, v8
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vmsne.vi v8, v9, 0
+; VLA-NEXT: vsm.v v8, (a0)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v2i1_nxv2i1_2:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v8, 2
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v0, v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v9, 0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.v v9, v8
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v8, v9, 0
-; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a0)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v2i1_nxv2i1_2:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; VLS-NEXT: vslidedown.vi v8, v8, 2
+; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLS-NEXT: vmsne.vi v0, v8, 0
+; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vmv.v.i v9, 0
+; VLS-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; VLS-NEXT: vmv.v.v v9, v8
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vmsne.vi v8, v9, 0
+; VLS-NEXT: vsm.v v8, (a0)
+; VLS-NEXT: ret
%c = call <2 x i1> @llvm.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 2)
store <2 x i1> %c, ptr %y
ret void
@@ -754,91 +760,91 @@ define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, ptr %y) {
}
define void @extract_v2i1_nxv64i1_42(<vscale x 64 x i1> %x, ptr %y) {
-; CHECK-V-LABEL: extract_v2i1_nxv64i1_42:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: vsetvli a1, zero, e8, m8, ta, ma
-; CHECK-V-NEXT: vmv.v.i v8, 0
-; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-V-NEXT: li a1, 42
-; CHECK-V-NEXT: vsetivli zero, 2, e8, m4, ta, ma
-; CHECK-V-NEXT: vslidedown.vx v8, v8, a1
-; CHECK-V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-V-NEXT: vmsne.vi v0, v8, 0
-; CHECK-V-NEXT: vmv.v.i v8, 0
-; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vmv.v.i v9, 0
-; CHECK-V-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-V-NEXT: vmv.v.v v9, v8
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vmsne.vi v8, v9, 0
-; CHECK-V-NEXT: vsm.v v8, (a0)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v2i1_nxv64i1_42:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetvli a1, zero, e8, m8, ta, ma
+; VLA-NEXT: vmv.v.i v8, 0
+; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: li a1, 42
+; VLA-NEXT: vsetivli zero, 2, e8, m4, ta, ma
+; VLA-NEXT: vslidedown.vx v8, v8, a1
+; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLA-NEXT: vmsne.vi v0, v8, 0
+; VLA-NEXT: vmv.v.i v8, 0
+; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vmv.v.i v9, 0
+; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; VLA-NEXT: vmv.v.v v9, v8
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vmsne.vi v8, v9, 0
+; VLA-NEXT: vsm.v v8, (a0)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v2i1_nxv64i1_42:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vsetvli a1, zero, e8, m8, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, m1, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v10, 10
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v0, v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v9, 0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.v v9, v8
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v8, v9, 0
-; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a0)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v2i1_nxv64i1_42:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetvli a1, zero, e8, m8, ta, ma
+; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma
+; VLS-NEXT: vslidedown.vi v8, v10, 10
+; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLS-NEXT: vmsne.vi v0, v8, 0
+; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vmv.v.i v9, 0
+; VLS-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; VLS-NEXT: vmv.v.v v9, v8
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vmsne.vi v8, v9, 0
+; VLS-NEXT: vsm.v v8, (a0)
+; VLS-NEXT: ret
%c = call <2 x i1> @llvm.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 42)
store <2 x i1> %c, ptr %y
ret void
}
define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, ptr %y) {
-; CHECK-V-LABEL: extract_v2i1_nxv32i1_26:
-; CHECK-V: # %bb.0:
-; CHECK-V-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-V-NEXT: vmv.v.i v8, 0
-; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-V-NEXT: vsetivli zero, 2, e8, m2, ta, ma
-; CHECK-V-NEXT: vslidedown.vi v8, v8, 26
-; CHECK-V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-V-NEXT: vmsne.vi v0, v8, 0
-; CHECK-V-NEXT: vmv.v.i v8, 0
-; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vmv.v.i v9, 0
-; CHECK-V-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-V-NEXT: vmv.v.v v9, v8
-; CHECK-V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-V-NEXT: vmsne.vi v8, v9, 0
-; CHECK-V-NEXT: vsm.v v8, (a0)
-; CHECK-V-NEXT: ret
+; VLA-LABEL: extract_v2i1_nxv32i1_26:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; VLA-NEXT: vmv.v.i v8, 0
+; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vsetivli zero, 2, e8, m2, ta, ma
+; VLA-NEXT: vslidedown.vi v8, v8, 26
+; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLA-NEXT: vmsne.vi v0, v8, 0
+; VLA-NEXT: vmv.v.i v8, 0
+; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vmv.v.i v9, 0
+; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; VLA-NEXT: vmv.v.v v9, v8
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vmsne.vi v8, v9, 0
+; VLA-NEXT: vsm.v v8, (a0)
+; VLA-NEXT: ret
;
-; CHECK-KNOWNVLEN128-LABEL: extract_v2i1_nxv32i1_26:
-; CHECK-KNOWNVLEN128: # %bb.0:
-; CHECK-KNOWNVLEN128-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, m1, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v9, 10
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v0, v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v8, 0
-; CHECK-KNOWNVLEN128-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.i v9, 0
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-KNOWNVLEN128-NEXT: vmv.v.v v9, v8
-; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-KNOWNVLEN128-NEXT: vmsne.vi v8, v9, 0
-; CHECK-KNOWNVLEN128-NEXT: vsm.v v8, (a0)
-; CHECK-KNOWNVLEN128-NEXT: ret
+; VLS-LABEL: extract_v2i1_nxv32i1_26:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma
+; VLS-NEXT: vslidedown.vi v8, v9, 10
+; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLS-NEXT: vmsne.vi v0, v8, 0
+; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vmv.v.i v9, 0
+; VLS-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; VLS-NEXT: vmv.v.v v9, v8
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vmsne.vi v8, v9, 0
+; VLS-NEXT: vsm.v v8, (a0)
+; VLS-NEXT: ret
%c = call <2 x i1> @llvm.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %x, i64 26)
store <2 x i1> %c, ptr %y
ret void
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
index efb1f720f2d096..9f0240c53b219a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
@@ -1,9 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV32VLA
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV64VLA
-; RUN: llc -mtriple=riscv32 -mattr=+m,+v -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV32VLA
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA,RV64VLA
+
+; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS,RV32VLS %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS,RV64VLS %s
define <vscale x 8 x i32> @insert_nxv8i32_v2i32_0(<vscale x 8 x i32> %vec, ptr %svp) {
; CHECK-LABEL: insert_nxv8i32_v2i32_0:
@@ -45,26 +48,40 @@ define <vscale x 8 x i32> @insert_nxv8i32_v2i32_6(<vscale x 8 x i32> %vec, ptr %
}
define <vscale x 8 x i32> @insert_nxv8i32_v8i32_0(<vscale x 8 x i32> %vec, ptr %svp) {
-; CHECK-LABEL: insert_nxv8i32_v8i32_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vle32.v v12, (a0)
-; CHECK-NEXT: vsetivli zero, 8, e32, m4, tu, ma
-; CHECK-NEXT: vmv.v.v v8, v12
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_nxv8i32_v8i32_0:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vle32.v v12, (a0)
+; VLA-NEXT: vsetivli zero, 8, e32, m4, tu, ma
+; VLA-NEXT: vmv.v.v v8, v12
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_nxv8i32_v8i32_0:
+; VLS: # %bb.0:
+; VLS-NEXT: vl2re32.v v12, (a0)
+; VLS-NEXT: vsetivli zero, 8, e32, m4, tu, ma
+; VLS-NEXT: vmv.v.v v8, v12
+; VLS-NEXT: ret
%sv = load <8 x i32>, ptr %svp
%v = call <vscale x 8 x i32> @llvm.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 0)
ret <vscale x 8 x i32> %v
}
define <vscale x 8 x i32> @insert_nxv8i32_v8i32_8(<vscale x 8 x i32> %vec, ptr %svp) {
-; CHECK-LABEL: insert_nxv8i32_v8i32_8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vle32.v v12, (a0)
-; CHECK-NEXT: vsetivli zero, 16, e32, m4, tu, ma
-; CHECK-NEXT: vslideup.vi v8, v12, 8
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_nxv8i32_v8i32_8:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vle32.v v12, (a0)
+; VLA-NEXT: vsetivli zero, 16, e32, m4, tu, ma
+; VLA-NEXT: vslideup.vi v8, v12, 8
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_nxv8i32_v8i32_8:
+; VLS: # %bb.0:
+; VLS-NEXT: vl2re32.v v12, (a0)
+; VLS-NEXT: vsetivli zero, 16, e32, m4, tu, ma
+; VLS-NEXT: vslideup.vi v8, v12, 8
+; VLS-NEXT: ret
%sv = load <8 x i32>, ptr %svp
%v = call <vscale x 8 x i32> @llvm.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 8)
ret <vscale x 8 x i32> %v
@@ -82,17 +99,27 @@ define <vscale x 8 x i32> @insert_nxv8i32_undef_v2i32_0(ptr %svp) {
}
define void @insert_v4i32_v2i32_0(ptr %vp, ptr %svp) {
-; CHECK-LABEL: insert_v4i32_v2i32_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vle32.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
-; CHECK-NEXT: vmv.v.v v9, v8
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vse32.v v9, (a0)
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_v4i32_v2i32_0:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLA-NEXT: vle32.v v8, (a1)
+; VLA-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; VLA-NEXT: vle32.v v9, (a0)
+; VLA-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; VLA-NEXT: vmv.v.v v9, v8
+; VLA-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; VLA-NEXT: vse32.v v9, (a0)
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_v4i32_v2i32_0:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLS-NEXT: vle32.v v8, (a1)
+; VLS-NEXT: vl1re32.v v9, (a0)
+; VLS-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; VLS-NEXT: vmv.v.v v9, v8
+; VLS-NEXT: vs1r.v v9, (a0)
+; VLS-NEXT: ret
%sv = load <2 x i32>, ptr %svp
%vec = load <4 x i32>, ptr %vp
%v = call <4 x i32> @llvm.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 0)
@@ -101,15 +128,25 @@ define void @insert_v4i32_v2i32_0(ptr %vp, ptr %svp) {
}
define void @insert_v4i32_v2i32_2(ptr %vp, ptr %svp) {
-; CHECK-LABEL: insert_v4i32_v2i32_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vle32.v v9, (a0)
-; CHECK-NEXT: vslideup.vi v9, v8, 2
-; CHECK-NEXT: vse32.v v9, (a0)
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_v4i32_v2i32_2:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLA-NEXT: vle32.v v8, (a1)
+; VLA-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; VLA-NEXT: vle32.v v9, (a0)
+; VLA-NEXT: vslideup.vi v9, v8, 2
+; VLA-NEXT: vse32.v v9, (a0)
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_v4i32_v2i32_2:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLS-NEXT: vle32.v v8, (a1)
+; VLS-NEXT: vl1re32.v v9, (a0)
+; VLS-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; VLS-NEXT: vslideup.vi v9, v8, 2
+; VLS-NEXT: vs1r.v v9, (a0)
+; VLS-NEXT: ret
%sv = load <2 x i32>, ptr %svp
%vec = load <4 x i32>, ptr %vp
%v = call <4 x i32> @llvm.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 2)
@@ -118,13 +155,20 @@ define void @insert_v4i32_v2i32_2(ptr %vp, ptr %svp) {
}
define void @insert_v4i32_undef_v2i32_0(ptr %vp, ptr %svp) {
-; CHECK-LABEL: insert_v4i32_undef_v2i32_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vse32.v v8, (a0)
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_v4i32_undef_v2i32_0:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLA-NEXT: vle32.v v8, (a1)
+; VLA-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; VLA-NEXT: vse32.v v8, (a0)
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_v4i32_undef_v2i32_0:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLS-NEXT: vle32.v v8, (a1)
+; VLS-NEXT: vs1r.v v8, (a0)
+; VLS-NEXT: ret
%sv = load <2 x i32>, ptr %svp
%v = call <4 x i32> @llvm.vector.insert.v2i32.v4i32(<4 x i32> undef, <2 x i32> %sv, i64 0)
store <4 x i32> %v, ptr %vp
@@ -132,17 +176,27 @@ define void @insert_v4i32_undef_v2i32_0(ptr %vp, ptr %svp) {
}
define void @insert_v8i32_v2i32_0(ptr %vp, ptr %svp) {
-; CHECK-LABEL: insert_v8i32_v2i32_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a0)
-; CHECK-NEXT: vsetivli zero, 2, e32, m2, tu, ma
-; CHECK-NEXT: vmv.v.v v10, v8
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vse32.v v10, (a0)
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_v8i32_v2i32_0:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLA-NEXT: vle32.v v8, (a1)
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vle32.v v10, (a0)
+; VLA-NEXT: vsetivli zero, 2, e32, m2, tu, ma
+; VLA-NEXT: vmv.v.v v10, v8
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vse32.v v10, (a0)
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_v8i32_v2i32_0:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLS-NEXT: vle32.v v8, (a1)
+; VLS-NEXT: vl2re32.v v10, (a0)
+; VLS-NEXT: vsetivli zero, 2, e32, m2, tu, ma
+; VLS-NEXT: vmv.v.v v10, v8
+; VLS-NEXT: vs2r.v v10, (a0)
+; VLS-NEXT: ret
%sv = load <2 x i32>, ptr %svp
%vec = load <8 x i32>, ptr %vp
%v = call <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 0)
@@ -151,17 +205,27 @@ define void @insert_v8i32_v2i32_0(ptr %vp, ptr %svp) {
}
define void @insert_v8i32_v2i32_2(ptr %vp, ptr %svp) {
-; CHECK-LABEL: insert_v8i32_v2i32_2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a0)
-; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, ma
-; CHECK-NEXT: vslideup.vi v10, v8, 2
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vse32.v v10, (a0)
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_v8i32_v2i32_2:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLA-NEXT: vle32.v v8, (a1)
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vle32.v v10, (a0)
+; VLA-NEXT: vsetivli zero, 4, e32, m2, tu, ma
+; VLA-NEXT: vslideup.vi v10, v8, 2
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vse32.v v10, (a0)
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_v8i32_v2i32_2:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLS-NEXT: vl2re32.v v8, (a0)
+; VLS-NEXT: vle32.v v10, (a1)
+; VLS-NEXT: vsetivli zero, 4, e32, m2, tu, ma
+; VLS-NEXT: vslideup.vi v8, v10, 2
+; VLS-NEXT: vs2r.v v8, (a0)
+; VLS-NEXT: ret
%sv = load <2 x i32>, ptr %svp
%vec = load <8 x i32>, ptr %vp
%v = call <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 2)
@@ -170,15 +234,25 @@ define void @insert_v8i32_v2i32_2(ptr %vp, ptr %svp) {
}
define void @insert_v8i32_v2i32_6(ptr %vp, ptr %svp) {
-; CHECK-LABEL: insert_v8i32_v2i32_6:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a0)
-; CHECK-NEXT: vslideup.vi v10, v8, 6
-; CHECK-NEXT: vse32.v v10, (a0)
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_v8i32_v2i32_6:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLA-NEXT: vle32.v v8, (a1)
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vle32.v v10, (a0)
+; VLA-NEXT: vslideup.vi v10, v8, 6
+; VLA-NEXT: vse32.v v10, (a0)
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_v8i32_v2i32_6:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLS-NEXT: vl2re32.v v8, (a0)
+; VLS-NEXT: vle32.v v10, (a1)
+; VLS-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLS-NEXT: vslideup.vi v8, v10, 6
+; VLS-NEXT: vs2r.v v8, (a0)
+; VLS-NEXT: ret
%sv = load <2 x i32>, ptr %svp
%vec = load <8 x i32>, ptr %vp
%v = call <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 6)
@@ -187,14 +261,23 @@ define void @insert_v8i32_v2i32_6(ptr %vp, ptr %svp) {
}
define void @insert_v8i32_undef_v2i32_6(ptr %vp, ptr %svp) {
-; CHECK-LABEL: insert_v8i32_undef_v2i32_6:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v8, 6
-; CHECK-NEXT: vse32.v v10, (a0)
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_v8i32_undef_v2i32_6:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLA-NEXT: vle32.v v8, (a1)
+; VLA-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLA-NEXT: vslideup.vi v10, v8, 6
+; VLA-NEXT: vse32.v v10, (a0)
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_v8i32_undef_v2i32_6:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; VLS-NEXT: vle32.v v8, (a1)
+; VLS-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; VLS-NEXT: vslideup.vi v10, v8, 6
+; VLS-NEXT: vs2r.v v10, (a0)
+; VLS-NEXT: ret
%sv = load <2 x i32>, ptr %svp
%v = call <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32> undef, <2 x i32> %sv, i64 6)
store <8 x i32> %v, ptr %vp
@@ -239,18 +322,30 @@ define void @insert_v4i16_v2i16_2(ptr %vp, ptr %svp) {
}
define void @insert_v32i1_v8i1_0(ptr %vp, ptr %svp) {
-; CHECK-LABEL: insert_v32i1_v8i1_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 32
-; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma
-; CHECK-NEXT: vlm.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vlm.v v9, (a1)
-; CHECK-NEXT: vsetivli zero, 1, e8, mf4, tu, ma
-; CHECK-NEXT: vmv.v.v v8, v9
-; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma
-; CHECK-NEXT: vsm.v v8, (a0)
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_v32i1_v8i1_0:
+; VLA: # %bb.0:
+; VLA-NEXT: li a2, 32
+; VLA-NEXT: vsetvli zero, a2, e8, m2, ta, ma
+; VLA-NEXT: vlm.v v8, (a0)
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vlm.v v9, (a1)
+; VLA-NEXT: vsetivli zero, 1, e8, mf4, tu, ma
+; VLA-NEXT: vmv.v.v v8, v9
+; VLA-NEXT: vsetvli zero, a2, e8, m2, ta, ma
+; VLA-NEXT: vsm.v v8, (a0)
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_v32i1_v8i1_0:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; VLS-NEXT: vlm.v v8, (a0)
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vlm.v v9, (a1)
+; VLS-NEXT: vsetivli zero, 1, e8, mf4, tu, ma
+; VLS-NEXT: vmv.v.v v8, v9
+; VLS-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; VLS-NEXT: vsm.v v8, (a0)
+; VLS-NEXT: ret
%v = load <32 x i1>, ptr %vp
%sv = load <8 x i1>, ptr %svp
%c = call <32 x i1> @llvm.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 0)
@@ -259,18 +354,30 @@ define void @insert_v32i1_v8i1_0(ptr %vp, ptr %svp) {
}
define void @insert_v32i1_v8i1_16(ptr %vp, ptr %svp) {
-; CHECK-LABEL: insert_v32i1_v8i1_16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 32
-; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma
-; CHECK-NEXT: vlm.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vlm.v v9, (a1)
-; CHECK-NEXT: vsetivli zero, 3, e8, mf4, tu, ma
-; CHECK-NEXT: vslideup.vi v8, v9, 2
-; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma
-; CHECK-NEXT: vsm.v v8, (a0)
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_v32i1_v8i1_16:
+; VLA: # %bb.0:
+; VLA-NEXT: li a2, 32
+; VLA-NEXT: vsetvli zero, a2, e8, m2, ta, ma
+; VLA-NEXT: vlm.v v8, (a0)
+; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLA-NEXT: vlm.v v9, (a1)
+; VLA-NEXT: vsetivli zero, 3, e8, mf4, tu, ma
+; VLA-NEXT: vslideup.vi v8, v9, 2
+; VLA-NEXT: vsetvli zero, a2, e8, m2, ta, ma
+; VLA-NEXT: vsm.v v8, (a0)
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_v32i1_v8i1_16:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; VLS-NEXT: vlm.v v8, (a0)
+; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; VLS-NEXT: vlm.v v9, (a1)
+; VLS-NEXT: vsetivli zero, 3, e8, mf4, tu, ma
+; VLS-NEXT: vslideup.vi v8, v9, 2
+; VLS-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; VLS-NEXT: vsm.v v8, (a0)
+; VLS-NEXT: ret
%v = load <32 x i1>, ptr %vp
%sv = load <8 x i1>, ptr %svp
%c = call <32 x i1> @llvm.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 16)
@@ -358,22 +465,36 @@ define <vscale x 2 x i16> @insert_nxv2i16_v2i16_2(<vscale x 2 x i16> %v, ptr %sv
}
define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, ptr %svp) {
-; CHECK-LABEL: insert_nxv2i1_v4i1_0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vlm.v v8, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, ma
-; CHECK-NEXT: vmv.v.v v9, v8
-; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmsne.vi v0, v9, 0
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_nxv2i1_v4i1_0:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; VLA-NEXT: vlm.v v8, (a0)
+; VLA-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; VLA-NEXT: vmv.v.i v9, 0
+; VLA-NEXT: vmerge.vim v9, v9, 1, v0
+; VLA-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; VLA-NEXT: vmv.v.i v10, 0
+; VLA-NEXT: vmv1r.v v0, v8
+; VLA-NEXT: vmerge.vim v8, v10, 1, v0
+; VLA-NEXT: vsetvli zero, zero, e8, mf4, tu, ma
+; VLA-NEXT: vmv.v.v v9, v8
+; VLA-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; VLA-NEXT: vmsne.vi v0, v9, 0
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_nxv2i1_v4i1_0:
+; VLS: # %bb.0:
+; VLS-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; VLS-NEXT: vlm.v v8, (a0)
+; VLS-NEXT: vmv.v.i v9, 0
+; VLS-NEXT: vmerge.vim v10, v9, 1, v0
+; VLS-NEXT: vmv1r.v v0, v8
+; VLS-NEXT: vmerge.vim v8, v9, 1, v0
+; VLS-NEXT: vsetvli zero, zero, e8, mf4, tu, ma
+; VLS-NEXT: vmv.v.v v10, v8
+; VLS-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; VLS-NEXT: vmsne.vi v0, v10, 0
+; VLS-NEXT: ret
%sv = load <4 x i1>, ptr %svp
%c = call <vscale x 2 x i1> @llvm.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1> %v, <4 x i1> %sv, i64 0)
ret <vscale x 2 x i1> %c
@@ -408,15 +529,24 @@ define <vscale x 8 x i1> @insert_nxv8i1_v8i1_16(<vscale x 8 x i1> %v, ptr %svp)
declare <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64>, <2 x i64>, i64)
define void @insert_v2i64_nxv16i64(ptr %psv0, ptr %psv1, ptr %out) {
-; CHECK-LABEL: insert_v2i64_nxv16i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vle64.v v16, (a1)
-; CHECK-NEXT: vsetivli zero, 6, e64, m8, tu, ma
-; CHECK-NEXT: vslideup.vi v8, v16, 4
-; CHECK-NEXT: vs8r.v v8, (a2)
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_v2i64_nxv16i64:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; VLA-NEXT: vle64.v v8, (a0)
+; VLA-NEXT: vle64.v v16, (a1)
+; VLA-NEXT: vsetivli zero, 6, e64, m8, tu, ma
+; VLA-NEXT: vslideup.vi v8, v16, 4
+; VLA-NEXT: vs8r.v v8, (a2)
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_v2i64_nxv16i64:
+; VLS: # %bb.0:
+; VLS-NEXT: vl1re64.v v8, (a0)
+; VLS-NEXT: vl1re64.v v16, (a1)
+; VLS-NEXT: vsetivli zero, 6, e64, m8, tu, ma
+; VLS-NEXT: vslideup.vi v8, v16, 4
+; VLS-NEXT: vs8r.v v8, (a2)
+; VLS-NEXT: ret
%sv0 = load <2 x i64>, ptr %psv0
%sv1 = load <2 x i64>, ptr %psv1
%v0 = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0)
@@ -426,12 +556,18 @@ define void @insert_v2i64_nxv16i64(ptr %psv0, ptr %psv1, ptr %out) {
}
define void @insert_v2i64_nxv16i64_lo0(ptr %psv, ptr %out) {
-; CHECK-LABEL: insert_v2i64_nxv16i64_lo0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vs8r.v v8, (a1)
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_v2i64_nxv16i64_lo0:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; VLA-NEXT: vle64.v v8, (a0)
+; VLA-NEXT: vs8r.v v8, (a1)
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_v2i64_nxv16i64_lo0:
+; VLS: # %bb.0:
+; VLS-NEXT: vl1re64.v v8, (a0)
+; VLS-NEXT: vs8r.v v8, (a1)
+; VLS-NEXT: ret
%sv = load <2 x i64>, ptr %psv
%v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 0)
store <vscale x 16 x i64> %v, ptr %out
@@ -439,14 +575,22 @@ define void @insert_v2i64_nxv16i64_lo0(ptr %psv, ptr %out) {
}
define void @insert_v2i64_nxv16i64_lo2(ptr %psv, ptr %out) {
-; CHECK-LABEL: insert_v2i64_nxv16i64_lo2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 4, e64, m8, ta, ma
-; CHECK-NEXT: vslideup.vi v16, v8, 2
-; CHECK-NEXT: vs8r.v v16, (a1)
-; CHECK-NEXT: ret
+; VLA-LABEL: insert_v2i64_nxv16i64_lo2:
+; VLA: # %bb.0:
+; VLA-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; VLA-NEXT: vle64.v v8, (a0)
+; VLA-NEXT: vsetivli zero, 4, e64, m8, ta, ma
+; VLA-NEXT: vslideup.vi v16, v8, 2
+; VLA-NEXT: vs8r.v v16, (a1)
+; VLA-NEXT: ret
+;
+; VLS-LABEL: insert_v2i64_nxv16i64_lo2:
+; VLS: # %bb.0:
+; VLS-NEXT: vl1re64.v v8, (a0)
+; VLS-NEXT: vsetivli zero, 4, e64, m8, ta, ma
+; VLS-NEXT: vslideup.vi v16, v8, 2
+; VLS-NEXT: vs8r.v v16, (a1)
+; VLS-NEXT: ret
%sv = load <2 x i64>, ptr %psv
%v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2)
store <vscale x 16 x i64> %v, ptr %out
@@ -521,6 +665,127 @@ define void @insert_v2i64_nxv16i64_hi(ptr %psv, ptr %out) {
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 80
; RV64-NEXT: ret
+; RV32VLA-LABEL: insert_v2i64_nxv16i64_hi:
+; RV32VLA: # %bb.0:
+; RV32VLA-NEXT: addi sp, sp, -80
+; RV32VLA-NEXT: .cfi_def_cfa_offset 80
+; RV32VLA-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
+; RV32VLA-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
+; RV32VLA-NEXT: .cfi_offset ra, -4
+; RV32VLA-NEXT: .cfi_offset s0, -8
+; RV32VLA-NEXT: addi s0, sp, 80
+; RV32VLA-NEXT: .cfi_def_cfa s0, 0
+; RV32VLA-NEXT: csrr a2, vlenb
+; RV32VLA-NEXT: slli a2, a2, 4
+; RV32VLA-NEXT: sub sp, sp, a2
+; RV32VLA-NEXT: andi sp, sp, -64
+; RV32VLA-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV32VLA-NEXT: vle64.v v8, (a0)
+; RV32VLA-NEXT: addi a0, sp, 128
+; RV32VLA-NEXT: vse64.v v8, (a0)
+; RV32VLA-NEXT: csrr a0, vlenb
+; RV32VLA-NEXT: slli a0, a0, 3
+; RV32VLA-NEXT: addi a2, sp, 64
+; RV32VLA-NEXT: add a3, a2, a0
+; RV32VLA-NEXT: vl8re64.v v8, (a3)
+; RV32VLA-NEXT: vl8re64.v v16, (a2)
+; RV32VLA-NEXT: add a0, a1, a0
+; RV32VLA-NEXT: vs8r.v v8, (a0)
+; RV32VLA-NEXT: vs8r.v v16, (a1)
+; RV32VLA-NEXT: addi sp, s0, -80
+; RV32VLA-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
+; RV32VLA-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
+; RV32VLA-NEXT: addi sp, sp, 80
+; RV32VLA-NEXT: ret
+;
+; RV64VLA-LABEL: insert_v2i64_nxv16i64_hi:
+; RV64VLA: # %bb.0:
+; RV64VLA-NEXT: addi sp, sp, -80
+; RV64VLA-NEXT: .cfi_def_cfa_offset 80
+; RV64VLA-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; RV64VLA-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; RV64VLA-NEXT: .cfi_offset ra, -8
+; RV64VLA-NEXT: .cfi_offset s0, -16
+; RV64VLA-NEXT: addi s0, sp, 80
+; RV64VLA-NEXT: .cfi_def_cfa s0, 0
+; RV64VLA-NEXT: csrr a2, vlenb
+; RV64VLA-NEXT: slli a2, a2, 4
+; RV64VLA-NEXT: sub sp, sp, a2
+; RV64VLA-NEXT: andi sp, sp, -64
+; RV64VLA-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV64VLA-NEXT: vle64.v v8, (a0)
+; RV64VLA-NEXT: addi a0, sp, 128
+; RV64VLA-NEXT: vse64.v v8, (a0)
+; RV64VLA-NEXT: csrr a0, vlenb
+; RV64VLA-NEXT: slli a0, a0, 3
+; RV64VLA-NEXT: addi a2, sp, 64
+; RV64VLA-NEXT: add a3, a2, a0
+; RV64VLA-NEXT: vl8re64.v v8, (a3)
+; RV64VLA-NEXT: vl8re64.v v16, (a2)
+; RV64VLA-NEXT: add a0, a1, a0
+; RV64VLA-NEXT: vs8r.v v8, (a0)
+; RV64VLA-NEXT: vs8r.v v16, (a1)
+; RV64VLA-NEXT: addi sp, s0, -80
+; RV64VLA-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; RV64VLA-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; RV64VLA-NEXT: addi sp, sp, 80
+; RV64VLA-NEXT: ret
+;
+; RV32VLS-LABEL: insert_v2i64_nxv16i64_hi:
+; RV32VLS: # %bb.0:
+; RV32VLS-NEXT: addi sp, sp, -80
+; RV32VLS-NEXT: .cfi_def_cfa_offset 80
+; RV32VLS-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
+; RV32VLS-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
+; RV32VLS-NEXT: .cfi_offset ra, -4
+; RV32VLS-NEXT: .cfi_offset s0, -8
+; RV32VLS-NEXT: addi s0, sp, 80
+; RV32VLS-NEXT: .cfi_def_cfa s0, 0
+; RV32VLS-NEXT: addi sp, sp, -256
+; RV32VLS-NEXT: andi sp, sp, -64
+; RV32VLS-NEXT: vl1re64.v v8, (a0)
+; RV32VLS-NEXT: addi a0, sp, 128
+; RV32VLS-NEXT: vs1r.v v8, (a0)
+; RV32VLS-NEXT: addi a0, sp, 64
+; RV32VLS-NEXT: addi a2, sp, 192
+; RV32VLS-NEXT: vl8re64.v v8, (a2)
+; RV32VLS-NEXT: vl8re64.v v16, (a0)
+; RV32VLS-NEXT: addi a0, a1, 128
+; RV32VLS-NEXT: vs8r.v v8, (a0)
+; RV32VLS-NEXT: vs8r.v v16, (a1)
+; RV32VLS-NEXT: addi sp, s0, -80
+; RV32VLS-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
+; RV32VLS-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
+; RV32VLS-NEXT: addi sp, sp, 80
+; RV32VLS-NEXT: ret
+;
+; RV64VLS-LABEL: insert_v2i64_nxv16i64_hi:
+; RV64VLS: # %bb.0:
+; RV64VLS-NEXT: addi sp, sp, -80
+; RV64VLS-NEXT: .cfi_def_cfa_offset 80
+; RV64VLS-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; RV64VLS-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; RV64VLS-NEXT: .cfi_offset ra, -8
+; RV64VLS-NEXT: .cfi_offset s0, -16
+; RV64VLS-NEXT: addi s0, sp, 80
+; RV64VLS-NEXT: .cfi_def_cfa s0, 0
+; RV64VLS-NEXT: addi sp, sp, -256
+; RV64VLS-NEXT: andi sp, sp, -64
+; RV64VLS-NEXT: vl1re64.v v8, (a0)
+; RV64VLS-NEXT: addi a0, sp, 128
+; RV64VLS-NEXT: vs1r.v v8, (a0)
+; RV64VLS-NEXT: addi a0, sp, 192
+; RV64VLS-NEXT: vl8re64.v v8, (a0)
+; RV64VLS-NEXT: addi a0, sp, 64
+; RV64VLS-NEXT: vl8re64.v v16, (a0)
+; RV64VLS-NEXT: addi a0, a1, 128
+; RV64VLS-NEXT: vs8r.v v8, (a0)
+; RV64VLS-NEXT: vs8r.v v16, (a1)
+; RV64VLS-NEXT: addi sp, s0, -80
+; RV64VLS-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; RV64VLS-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; RV64VLS-NEXT: addi sp, sp, 80
+; RV64VLS-NEXT: ret
%sv = load <2 x i64>, ptr %psv
%v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 8)
store <vscale x 16 x i64> %v, ptr %out
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
index 6ef5aa846d6d96..ce8827fe47536b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
@@ -1,6 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLA %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLA %s
+
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS %s
define <8 x i32> @concat_2xv4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: concat_2xv4i32:
@@ -128,31 +131,51 @@ define <16 x i32> @concat_8xv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x
}
define <32 x i32> @concat_2xv16i32(<16 x i32> %a, <16 x i32> %b) {
-; CHECK-LABEL: concat_2xv16i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmv4r.v v16, v12
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v16, 16
-; CHECK-NEXT: ret
+; VLA-LABEL: concat_2xv16i32:
+; VLA: # %bb.0:
+; VLA-NEXT: vmv4r.v v16, v12
+; VLA-NEXT: li a0, 32
+; VLA-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; VLA-NEXT: vslideup.vi v8, v16, 16
+; VLA-NEXT: ret
+;
+; VLS-LABEL: concat_2xv16i32:
+; VLS: # %bb.0:
+; VLS-NEXT: vmv4r.v v16, v12
+; VLS-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; VLS-NEXT: vslideup.vi v8, v16, 16
+; VLS-NEXT: ret
%ab = shufflevector <16 x i32> %a, <16 x i32> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
ret <32 x i32> %ab
}
define <32 x i32> @concat_4xv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) {
-; CHECK-LABEL: concat_4xv8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vmv2r.v v16, v14
-; CHECK-NEXT: vmv2r.v v24, v12
-; CHECK-NEXT: vmv2r.v v0, v10
-; CHECK-NEXT: vsetivli zero, 16, e32, m8, tu, ma
-; CHECK-NEXT: vslideup.vi v8, v0, 8
-; CHECK-NEXT: vsetivli zero, 24, e32, m8, tu, ma
-; CHECK-NEXT: vslideup.vi v8, v24, 16
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v16, 24
-; CHECK-NEXT: ret
+; VLA-LABEL: concat_4xv8i32:
+; VLA: # %bb.0:
+; VLA-NEXT: vmv2r.v v16, v14
+; VLA-NEXT: vmv2r.v v24, v12
+; VLA-NEXT: vmv2r.v v0, v10
+; VLA-NEXT: vsetivli zero, 16, e32, m8, tu, ma
+; VLA-NEXT: vslideup.vi v8, v0, 8
+; VLA-NEXT: vsetivli zero, 24, e32, m8, tu, ma
+; VLA-NEXT: vslideup.vi v8, v24, 16
+; VLA-NEXT: li a0, 32
+; VLA-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; VLA-NEXT: vslideup.vi v8, v16, 24
+; VLA-NEXT: ret
+;
+; VLS-LABEL: concat_4xv8i32:
+; VLS: # %bb.0:
+; VLS-NEXT: vmv2r.v v16, v14
+; VLS-NEXT: vmv2r.v v24, v12
+; VLS-NEXT: vmv2r.v v0, v10
+; VLS-NEXT: vsetivli zero, 16, e32, m8, tu, ma
+; VLS-NEXT: vslideup.vi v8, v0, 8
+; VLS-NEXT: vsetivli zero, 24, e32, m8, tu, ma
+; VLS-NEXT: vslideup.vi v8, v24, 16
+; VLS-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; VLS-NEXT: vslideup.vi v8, v16, 24
+; VLS-NEXT: ret
%ab = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%cd = shufflevector <8 x i32> %c, <8 x i32> %d, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%abcd = shufflevector <16 x i32> %ab, <16 x i32> %cd, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
@@ -160,82 +183,128 @@ define <32 x i32> @concat_4xv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x
}
define <32 x i32> @concat_8xv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f, <4 x i32> %g, <4 x i32> %h) {
-; CHECK-LABEL: concat_8xv4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; CHECK-NEXT: vmv1r.v v16, v15
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 0
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a1, a1, a0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
-; CHECK-NEXT: vmv1r.v v16, v14
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
-; CHECK-NEXT: vmv1r.v v16, v13
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
-; CHECK-NEXT: vmv1r.v v16, v12
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmv1r.v v24, v10
-; CHECK-NEXT: vmv1r.v v16, v9
-; CHECK-NEXT: vsetivli zero, 8, e32, m8, tu, ma
-; CHECK-NEXT: vslideup.vi v8, v16, 4
-; CHECK-NEXT: vsetivli zero, 12, e32, m8, tu, ma
-; CHECK-NEXT: vslideup.vi v8, v24, 8
-; CHECK-NEXT: vsetivli zero, 16, e32, m8, tu, ma
-; CHECK-NEXT: vslideup.vi v8, v0, 12
-; CHECK-NEXT: vsetivli zero, 20, e32, m8, tu, ma
-; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vslideup.vi v8, v16, 16
-; CHECK-NEXT: vsetivli zero, 24, e32, m8, tu, ma
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vslideup.vi v8, v16, 20
-; CHECK-NEXT: vsetivli zero, 28, e32, m8, tu, ma
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vslideup.vi v8, v16, 24
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 0
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a1, a1, a0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vslideup.vi v8, v16, 28
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; VLA-LABEL: concat_8xv4i32:
+; VLA: # %bb.0:
+; VLA-NEXT: addi sp, sp, -16
+; VLA-NEXT: .cfi_def_cfa_offset 16
+; VLA-NEXT: csrr a0, vlenb
+; VLA-NEXT: slli a0, a0, 5
+; VLA-NEXT: sub sp, sp, a0
+; VLA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; VLA-NEXT: vmv1r.v v16, v15
+; VLA-NEXT: csrr a0, vlenb
+; VLA-NEXT: li a1, 0
+; VLA-NEXT: slli a0, a0, 3
+; VLA-NEXT: add a1, a1, a0
+; VLA-NEXT: slli a0, a0, 1
+; VLA-NEXT: add a0, a0, a1
+; VLA-NEXT: add a0, sp, a0
+; VLA-NEXT: addi a0, a0, 16
+; VLA-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; VLA-NEXT: vmv1r.v v16, v14
+; VLA-NEXT: csrr a0, vlenb
+; VLA-NEXT: slli a0, a0, 4
+; VLA-NEXT: add a0, sp, a0
+; VLA-NEXT: addi a0, a0, 16
+; VLA-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; VLA-NEXT: vmv1r.v v16, v13
+; VLA-NEXT: csrr a0, vlenb
+; VLA-NEXT: slli a0, a0, 3
+; VLA-NEXT: add a0, sp, a0
+; VLA-NEXT: addi a0, a0, 16
+; VLA-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; VLA-NEXT: vmv1r.v v16, v12
+; VLA-NEXT: addi a0, sp, 16
+; VLA-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; VLA-NEXT: vmv1r.v v0, v11
+; VLA-NEXT: vmv1r.v v24, v10
+; VLA-NEXT: vmv1r.v v16, v9
+; VLA-NEXT: vsetivli zero, 8, e32, m8, tu, ma
+; VLA-NEXT: vslideup.vi v8, v16, 4
+; VLA-NEXT: vsetivli zero, 12, e32, m8, tu, ma
+; VLA-NEXT: vslideup.vi v8, v24, 8
+; VLA-NEXT: vsetivli zero, 16, e32, m8, tu, ma
+; VLA-NEXT: vslideup.vi v8, v0, 12
+; VLA-NEXT: vsetivli zero, 20, e32, m8, tu, ma
+; VLA-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; VLA-NEXT: vslideup.vi v8, v16, 16
+; VLA-NEXT: vsetivli zero, 24, e32, m8, tu, ma
+; VLA-NEXT: csrr a0, vlenb
+; VLA-NEXT: slli a0, a0, 3
+; VLA-NEXT: add a0, sp, a0
+; VLA-NEXT: addi a0, a0, 16
+; VLA-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; VLA-NEXT: vslideup.vi v8, v16, 20
+; VLA-NEXT: vsetivli zero, 28, e32, m8, tu, ma
+; VLA-NEXT: csrr a0, vlenb
+; VLA-NEXT: slli a0, a0, 4
+; VLA-NEXT: add a0, sp, a0
+; VLA-NEXT: addi a0, a0, 16
+; VLA-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; VLA-NEXT: vslideup.vi v8, v16, 24
+; VLA-NEXT: li a0, 32
+; VLA-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; VLA-NEXT: csrr a0, vlenb
+; VLA-NEXT: li a1, 0
+; VLA-NEXT: slli a0, a0, 3
+; VLA-NEXT: add a1, a1, a0
+; VLA-NEXT: slli a0, a0, 1
+; VLA-NEXT: add a0, a0, a1
+; VLA-NEXT: add a0, sp, a0
+; VLA-NEXT: addi a0, a0, 16
+; VLA-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; VLA-NEXT: vslideup.vi v8, v16, 28
+; VLA-NEXT: csrr a0, vlenb
+; VLA-NEXT: slli a0, a0, 5
+; VLA-NEXT: add sp, sp, a0
+; VLA-NEXT: addi sp, sp, 16
+; VLA-NEXT: ret
+;
+; VLS-LABEL: concat_8xv4i32:
+; VLS: # %bb.0:
+; VLS-NEXT: addi sp, sp, -16
+; VLS-NEXT: .cfi_def_cfa_offset 16
+; VLS-NEXT: addi sp, sp, -512
+; VLS-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; VLS-NEXT: vmv1r.v v16, v15
+; VLS-NEXT: addi a0, sp, 400
+; VLS-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; VLS-NEXT: vmv1r.v v16, v14
+; VLS-NEXT: addi a0, sp, 272
+; VLS-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; VLS-NEXT: vmv1r.v v16, v13
+; VLS-NEXT: addi a0, sp, 144
+; VLS-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; VLS-NEXT: vmv1r.v v16, v12
+; VLS-NEXT: addi a0, sp, 16
+; VLS-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; VLS-NEXT: vmv1r.v v0, v11
+; VLS-NEXT: vmv1r.v v24, v10
+; VLS-NEXT: vmv1r.v v16, v9
+; VLS-NEXT: vsetivli zero, 8, e32, m8, tu, ma
+; VLS-NEXT: vslideup.vi v8, v16, 4
+; VLS-NEXT: vsetivli zero, 12, e32, m8, tu, ma
+; VLS-NEXT: vslideup.vi v8, v24, 8
+; VLS-NEXT: vsetivli zero, 16, e32, m8, tu, ma
+; VLS-NEXT: vslideup.vi v8, v0, 12
+; VLS-NEXT: vsetivli zero, 20, e32, m8, tu, ma
+; VLS-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; VLS-NEXT: vslideup.vi v8, v16, 16
+; VLS-NEXT: vsetivli zero, 24, e32, m8, tu, ma
+; VLS-NEXT: addi a0, sp, 144
+; VLS-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; VLS-NEXT: vslideup.vi v8, v16, 20
+; VLS-NEXT: vsetivli zero, 28, e32, m8, tu, ma
+; VLS-NEXT: addi a0, sp, 272
+; VLS-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; VLS-NEXT: vslideup.vi v8, v16, 24
+; VLS-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; VLS-NEXT: addi a0, sp, 400
+; VLS-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; VLS-NEXT: vslideup.vi v8, v16, 28
+; VLS-NEXT: addi sp, sp, 512
+; VLS-NEXT: addi sp, sp, 16
+; VLS-NEXT: ret
%ab = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%cd = shufflevector <4 x i32> %c, <4 x i32> %d, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%abcd = shufflevector <8 x i32> %ab, <8 x i32> %cd, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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