[llvm] [AMDGPU] Do not attempt to fallback to default mutations (PR #83208)
Jeffrey Byrnes via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 27 15:37:57 PST 2024
https://github.com/jrbyrnes created https://github.com/llvm/llvm-project/pull/83208
IGLP itself will be in SavedMutations via mutations added during Scheduler creation, thus falling back results in reapplying IGLP.
In PostRA scheduling, if we have multiple regions with IGLP instructions, then we may have infinite loop.
Disable the feature for now.
>From 1c0b27d8744dc27b2325d128e8f32d4b48e8a81e Mon Sep 17 00:00:00 2001
From: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
Date: Tue, 27 Feb 2024 15:16:07 -0800
Subject: [PATCH] [AMDGPU] Do not attempt to fallback to default mutations
Change-Id: Id30319f933d8b0509bb9866cdb48b3f60e85a26f
---
llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp | 21 ++++---------------
llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h | 5 ++---
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 8 +++----
llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp | 10 ++++-----
llvm/test/CodeGen/AMDGPU/iglp.opt.reentry.ll | 15 +++++++++++++
5 files changed, 28 insertions(+), 31 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/iglp.opt.reentry.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index e3f72485079538..57769fe998d1fe 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -2337,8 +2337,6 @@ class IGroupLPDAGMutation : public ScheduleDAGMutation {
ScheduleDAGMI *DAG;
- std::vector<std::unique_ptr<ScheduleDAGMutation>> *SavedMutations;
-
// Organize lists of SchedGroups by their SyncID. SchedGroups /
// SCHED_GROUP_BARRIERs with different SyncIDs will have no edges added
// between then.
@@ -2381,10 +2379,7 @@ class IGroupLPDAGMutation : public ScheduleDAGMutation {
AMDGPU::SchedulingPhase Phase = AMDGPU::SchedulingPhase::Initial;
IGroupLPDAGMutation() = default;
- IGroupLPDAGMutation(
- AMDGPU::SchedulingPhase Phase,
- std::vector<std::unique_ptr<ScheduleDAGMutation>> *SavedMutations)
- : SavedMutations(SavedMutations), Phase(Phase) {}
+ IGroupLPDAGMutation(AMDGPU::SchedulingPhase Phase) : Phase(Phase) {}
};
unsigned SchedGroup::NumSchedGroups = 0;
@@ -2602,13 +2597,6 @@ void IGroupLPDAGMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
PS.solve();
return;
}
-
- if (!SavedMutations)
- return;
-
- // We did not apply a mutation, fall back to SavedMutations
- for (auto &m : *SavedMutations)
- m->apply(DAG);
}
void IGroupLPDAGMutation::addSchedBarrierEdges(SUnit &SchedBarrier) {
@@ -2707,10 +2695,9 @@ namespace llvm {
/// same scheduling region (e.g. pre and post-RA scheduling / multiple
/// scheduling "phases"), we can reenter this mutation framework more than once
/// for a given region.
-std::unique_ptr<ScheduleDAGMutation> createIGroupLPDAGMutation(
- AMDGPU::SchedulingPhase Phase,
- std::vector<std::unique_ptr<ScheduleDAGMutation>> *SavedMutations) {
- return std::make_unique<IGroupLPDAGMutation>(Phase, SavedMutations);
+std::unique_ptr<ScheduleDAGMutation>
+createIGroupLPDAGMutation(AMDGPU::SchedulingPhase Phase) {
+ return std::make_unique<IGroupLPDAGMutation>(Phase);
}
} // end namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h
index 46ef4d702d0022..aff7096f26d671 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h
@@ -20,9 +20,8 @@ namespace AMDGPU {
enum class SchedulingPhase { Initial, PreRAReentry, PostRA };
} // namespace AMDGPU
-std::unique_ptr<ScheduleDAGMutation> createIGroupLPDAGMutation(
- AMDGPU::SchedulingPhase Phase,
- std::vector<std::unique_ptr<ScheduleDAGMutation>> *SavedMutations);
+std::unique_ptr<ScheduleDAGMutation>
+createIGroupLPDAGMutation(AMDGPU::SchedulingPhase Phase);
} // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 0d830df1f1f1df..76e843455bab75 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -461,8 +461,7 @@ createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
if (ST.shouldClusterStores())
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
- DAG->addMutation(
- createIGroupLPDAGMutation(AMDGPU::SchedulingPhase::Initial, nullptr));
+ DAG->addMutation(createIGroupLPDAGMutation(AMDGPU::SchedulingPhase::Initial));
DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
return DAG;
@@ -472,8 +471,7 @@ static ScheduleDAGInstrs *
createGCNMaxILPMachineScheduler(MachineSchedContext *C) {
ScheduleDAGMILive *DAG =
new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxILPSchedStrategy>(C));
- DAG->addMutation(
- createIGroupLPDAGMutation(AMDGPU::SchedulingPhase::Initial, nullptr));
+ DAG->addMutation(createIGroupLPDAGMutation(AMDGPU::SchedulingPhase::Initial));
return DAG;
}
@@ -937,7 +935,7 @@ class GCNPassConfig final : public AMDGPUPassConfig {
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
DAG->addMutation(ST.createFillMFMAShadowMutation(DAG->TII));
DAG->addMutation(
- createIGroupLPDAGMutation(AMDGPU::SchedulingPhase::PostRA, nullptr));
+ createIGroupLPDAGMutation(AMDGPU::SchedulingPhase::PostRA));
if (isPassEnabled(EnableVOPD, CodeGenOptLevel::Less))
DAG->addMutation(createVOPDPairingMutation());
return DAG;
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index f993ec8409c997..9f419a7fbf6834 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -713,8 +713,8 @@ bool UnclusteredHighRPStage::initGCNSchedStage() {
return false;
SavedMutations.swap(DAG.Mutations);
- DAG.addMutation(createIGroupLPDAGMutation(
- AMDGPU::SchedulingPhase::PreRAReentry, nullptr));
+ DAG.addMutation(
+ createIGroupLPDAGMutation(AMDGPU::SchedulingPhase::PreRAReentry));
InitialOccupancy = DAG.MinOccupancy;
// Aggressivly try to reduce register pressure in the unclustered high RP
@@ -858,8 +858,7 @@ bool GCNSchedStage::initGCNRegion() {
StageID == GCNSchedStageID::ILPInitialSchedule;
DAG.addMutation(createIGroupLPDAGMutation(
IsInitialStage ? AMDGPU::SchedulingPhase::Initial
- : AMDGPU::SchedulingPhase::PreRAReentry,
- &SavedMutations));
+ : AMDGPU::SchedulingPhase::PreRAReentry));
}
return true;
@@ -1573,8 +1572,7 @@ void GCNPostScheduleDAGMILive::schedule() {
if (HasIGLPInstrs) {
SavedMutations.clear();
SavedMutations.swap(Mutations);
- addMutation(createIGroupLPDAGMutation(AMDGPU::SchedulingPhase::PostRA,
- &SavedMutations));
+ addMutation(createIGroupLPDAGMutation(AMDGPU::SchedulingPhase::PostRA));
}
ScheduleDAGMI::schedule();
diff --git a/llvm/test/CodeGen/AMDGPU/iglp.opt.reentry.ll b/llvm/test/CodeGen/AMDGPU/iglp.opt.reentry.ll
new file mode 100644
index 00000000000000..1113acb3c0305a
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/iglp.opt.reentry.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -O3 < %s | FileCheck %s
+
+; Test should not result in build failure
+; CHECK-LABEL: shouldNotReApply
+
+define amdgpu_kernel void @shouldNotReApply() {
+entry:
+ tail call void @llvm.amdgcn.sched.barrier(i32 0)
+ store <4 x i32> zeroinitializer, ptr addrspace(3) null, align 2147483648
+ tail call void @llvm.amdgcn.sched.group.barrier(i32 0, i32 0, i32 0)
+ tail call void @llvm.amdgcn.sched.barrier(i32 0)
+ store i32 0, ptr addrspace(5) null, align 2147483648
+ tail call void @llvm.amdgcn.sched.group.barrier(i32 0, i32 0, i32 0)
+ ret void
+}
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