[llvm] [llvm][arm] add T1 and T2 assembly options for vlldm and vlstm (PR #83116)

[via llvm-commits]

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@@ -183,6 +183,10 @@ def UseNegativeImmediates :
             AssemblerPredicate<(all_of (not FeatureNoNegativeImmediates)),
                                "NegativeImmediates">;
 
+def HasD32    : Predicate<"Subtarget->hasD32()">,
+                           AssemblerPredicate<(all_of FeatureD32),
+                           "32 D registers">;
+
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sivan-shani wrote:

It is used (HasD16 was not used and was removed)

https://github.com/llvm/llvm-project/pull/83116