[llvm] [llvm][arm] add T1 and T2 assembly options for vlldm and vlstm (PR #83116)

[Tomas Matheson via llvm-commits]

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@@ -7596,6 +7601,38 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
 
   const unsigned Opcode = Inst.getOpcode();
   switch (Opcode) {
+  case ARM::VLLDM:
+    [[fallthrough]];
+  case ARM::VLLDM_T2:
+    [[fallthrough]];
+  case ARM::VLSTM:
+    [[fallthrough]];
+  case ARM::VLSTM_T2: {
+    // Since in some cases both T1 and T2 are valid, tablegen can not always
+    // pick the correct instruction.
+    if (Operands.size() == 4) { // a register list has been provided
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tmatheson-arm wrote:

I think you will always have 4 operands, because you are doing the disassembly in `DecodeLazyLoadStoreMul`. This could be omitted, or made an assert.

https://github.com/llvm/llvm-project/pull/83116