[llvm] [llvm][arm] add T1 and T2 assembly options for vlldm and vlstm (PR #83116)

[Tomas Matheson via llvm-commits]

================
@@ -7030,3 +7033,26 @@ static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
 
   return DS;
 }
+
+static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn,
+                                           uint64_t Address,
+                                           const MCDisassembler *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+  // Adding Rn, holding memory location to save/load to/from, the only argument
+  // that being encoded.
+  // '$Rn' in the assembly.
+  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  // An optional predicate, '$p' in the assembly.
+  Inst.addOperand(MCOperand::createImm(0));
----------------
tmatheson-arm wrote:

If these are predicated you'll need to parse the predicate properly, using `DecodePredicateOperand`. Please also add tests for some predicated versions.

https://github.com/llvm/llvm-project/pull/83116