[llvm] [arm] add T1 and T2 assembly optoins for vlldm and vlstm (PR #83116)

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git-clang-format --diff b2ebd8b89777a1c5ba6acc4ad9f195ea2ad5f0de f55b2baddc26f4df0691fec0870f3ff2c06f5e1e -- llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp llvm/unittests/Target/ARM/MachineInstrTest.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 52ba64f20f..56a7bd3d69 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -454,7 +454,8 @@ class ARMAsmParser : public MCTargetAsmParser {
   bool tryParseRegisterWithWriteBack(OperandVector &);
   int tryParseShiftRegister(OperandVector &);
   bool parseRegisterList(OperandVector &, bool EnforceOrder = true,
-                         bool AllowRAAC = false, bool AllowOutOfBoundReg = false);
+                         bool AllowRAAC = false,
+                         bool AllowOutOfBoundReg = false);
   bool parseMemory(OperandVector &);
   bool parseOperand(OperandVector &, StringRef Mnemonic);
   bool parseImmExpr(int64_t &Out);
@@ -4116,7 +4117,8 @@ int ARMAsmParser::tryParseRegister(bool AllowOutOfBoundReg) {
   }
 
   // Some FPUs only have 16 D registers, so D16-D31 are invalid
-  if (!AllowOutOfBoundReg && !hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
+  if (!AllowOutOfBoundReg && !hasD32() && RegNum >= ARM::D16 &&
+      RegNum <= ARM::D31)
     return -1;
 
   Parser.Lex(); // Eat identifier token.
@@ -6087,7 +6089,8 @@ bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
     return parseMemory(Operands);
   case AsmToken::LCurly: {
     bool AllowOutOfBoundReg = Mnemonic == "vlldm" || Mnemonic == "vlstm";
-    return parseRegisterList(Operands, !Mnemonic.starts_with("clr"), false, AllowOutOfBoundReg);
+    return parseRegisterList(Operands, !Mnemonic.starts_with("clr"), false,
+                             AllowOutOfBoundReg);
   }
   case AsmToken::Dollar:
   case AsmToken::Hash: {
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 44f68646d0..70761b6a05 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -703,7 +703,7 @@ static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
 static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn,
                                            uint64_t Address,
                                            const MCDisassembler *Decoder);
-                                           
+
 #include "ARMGenDisassemblerTables.inc"
 
 static MCDisassembler *createARMDisassembler(const Target &T,

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https://github.com/llvm/llvm-project/pull/83116