[llvm] [RISCV] Recursively split concat_vector into smaller LMULs (PR #83035)

[Luke Lau via llvm-commits]

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@@ -15262,13 +15262,54 @@ static SDValue performINSERT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
   return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps);
 }
 
+// Recursively split up concat_vectors with more than 2 operands:
+//
+// concat_vector op1, op2, op3, op4
+// ->
+// concat_vector (concat_vector op1, op2), (concat_vector op3, op4)
+//
+// This reduces the length of the chain of vslideups and allows us to perform
+// the vslideups at a smaller LMUL.
+//
+// We do this as a DAG combine rather than during lowering so that any undef
+// operands can get combined away.
+static SDValue
+performCONCAT_VECTORSSplitCombine(SDNode *N, SelectionDAG &DAG,
+                                  const RISCVTargetLowering &TLI) {
+  SDLoc DL(N);
+
+  if (N->getNumOperands() <= 2)
+    return SDValue();
+
+  if (!TLI.isTypeLegal(N->getValueType(0)))
+    return SDValue();
+  MVT VT = N->getSimpleValueType(0);
+
+  MVT HalfVT = VT.getHalfNumVectorElementsVT();
+  size_t HalfNumOps = (N->getNumOperands() + 1) / 2;
----------------
lukel97 wrote:

HalfNumOps is used for the number of operands in each sub concat_vector, so `HalfVT.getVectorNumElements() == HalfNumOps * N->getOperand(0).getSimpleValueType().getVectorNumElements()`

And I believe `!TLI.isTypeLegal(N->getValueType(0))` should rule out any non-power-of-2-types. Which actually come to think of it should mean that `N->getNumOperands()` should always be a power of two as well?

https://github.com/llvm/llvm-project/pull/83035