[llvm] [PowerPC] provide CFI for ELF32 to unwind cr2, cr3, cr4 (PR #83098)

[George Koehler via llvm-commits]

https://github.com/kernigh created https://github.com/llvm/llvm-project/pull/83098

Delete the code that skips the CFI for the condition register on ELF32.  The code checked !MustSaveCR, which happened only when Subtarget.is32BitELFABI(), where spillCalleeSavedRegisters is spilling cr in a different way.  The spill was missing CFI.  After deleting this code, a spill of cr2 to cr4 gets CFI in the same way as a spill of r14 to r31.

Fixes #83094

>From 4cf34d7b7a82438aa5b2c148ca7a0b2b44f9e711 Mon Sep 17 00:00:00 2001
From: George Koehler <kernigh at gmail.com>
Date: Mon, 26 Feb 2024 21:08:26 -0500
Subject: [PATCH] [PowerPC] provide CFI for ELF32 to unwind cr2, cr3, cr4

Delete the code that skips the CFI for the condition register on
ELF32.  The code checked !MustSaveCR, which happened only when
Subtarget.is32BitELFABI(), where spillCalleeSavedRegisters is spilling
cr in a different way.  The spill was missing CFI.  After deleting
this code, a spill of cr2 to cr4 gets CFI in the same way as a spill
of r14 to r31.

Fixes #83094
---
 llvm/lib/Target/PowerPC/PPCFrameLowering.cpp |  6 ------
 llvm/test/CodeGen/PowerPC/crsave.ll          | 22 ++++++++++++--------
 2 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index 6792842f8550c1..424501c35c043c 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -1191,12 +1191,6 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
       if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
         continue;
 
-      // For SVR4, don't emit a move for the CR spill slot if we haven't
-      // spilled CRs.
-      if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
-          && !MustSaveCR)
-        continue;
-
       // For 64-bit SVR4 when we have spilled CRs, the spill location
       // is SP+8, not a frame-relative slot.
       if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
diff --git a/llvm/test/CodeGen/PowerPC/crsave.ll b/llvm/test/CodeGen/PowerPC/crsave.ll
index 81e7a0adcc8ca1..efa8b3f0120998 100644
--- a/llvm/test/CodeGen/PowerPC/crsave.ll
+++ b/llvm/test/CodeGen/PowerPC/crsave.ll
@@ -15,11 +15,12 @@ entry:
 }
 
 ; PPC32-LABEL: test_cr2:
-; PPC32: stwu 1, -32(1)
-; PPC32: stw 31, 28(1)
+; PPC32: stwu 1, -[[#%u,AMT:]](1)
+; PPC32: stw 31, [[#AMT - 4]](1)
+; PPC32: .cfi_offset cr2, -[[#%u,DOWN:]]
 ; PPC32: mfcr 12
-; PPC32-NEXT: stw 12, 24(31)
-; PPC32: lwz 12, 24(31)
+; PPC32-NEXT: stw 12, [[#AMT - DOWN]](31)
+; PPC32: lwz 12, [[#AMT - DOWN]](31)
 ; PPC32-NEXT: mtocrf 32, 12
 
 ; PPC64: .cfi_startproc
@@ -34,7 +35,7 @@ entry:
 ; PPC64: mtocrf 32, 12
 ; PPC64: .cfi_endproc
 
-define i32 @test_cr234() nounwind {
+define i32 @test_cr234() nounwind uwtable {
 entry:
   %ret = alloca i32, align 4
   %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmpw 2,$2,$1\0A\09cmpw 3,$2,$2\0A\09cmpw 4,$2,$3\0A\09mfcr $0", "=r,r,r,r,r,~{cr2},~{cr3},~{cr4}"(i32 1, i32 2, i32 3, i32 0) nounwind
@@ -45,11 +46,14 @@ entry:
 }
 
 ; PPC32-LABEL: test_cr234:
-; PPC32: stwu 1, -32(1)
-; PPC32: stw 31, 28(1)
+; PPC32: stwu 1, -[[#%u,AMT:]](1)
+; PPC32: stw 31, [[#AMT - 4]](1)
+; PPC32: .cfi_offset cr2, -[[#%u,DOWN:]]
+; PPC32: .cfi_offset cr3, -[[#DOWN]]
+; PPC32: .cfi_offset cr4, -[[#DOWN]]
 ; PPC32: mfcr 12
-; PPC32-NEXT: stw 12, 24(31)
-; PPC32: lwz 12, 24(31)
+; PPC32-NEXT: stw 12, [[#AMT - DOWN]](31)
+; PPC32: lwz 12, [[#AMT - DOWN]](31)
 ; PPC32-NEXT: mtocrf 32, 12
 ; PPC32-NEXT: mtocrf 16, 12
 ; PPC32-NEXT: mtocrf 8, 12