[llvm] [RISCV][MC] Implement ISA mapping symbols (PR #67541)
Joe Faulls via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 26 03:54:12 PST 2024
https://github.com/joe-img updated https://github.com/llvm/llvm-project/pull/67541
>From 578cf474d993caa5a56d2abe4b3a66b85a355a2b Mon Sep 17 00:00:00 2001
From: "Joseph.Faulls" <Joseph.Faulls at imgtec.com>
Date: Tue, 26 Sep 2023 16:49:00 +0100
Subject: [PATCH 1/7] [RISCV][MC] Implement ISA mapping symbols
$x<ISA> indicates the start of a sequence of instructions with <ISA>
extension [1].
[1]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#mapping-symbol
---
.../RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 16 ++++++-
.../RISCV/MCTargetDesc/RISCVELFStreamer.h | 5 +-
llvm/test/MC/RISCV/mapping-isa.s | 47 +++++++++++++++++++
3 files changed, 66 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/MC/RISCV/mapping-isa.s
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index 961b8f0afe2254..f5fd814eefad37 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -66,6 +66,7 @@ void RISCVTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
void RISCVTargetELFStreamer::emitTextAttribute(unsigned Attribute,
StringRef String) {
getStreamer().setAttributeItem(Attribute, String, /*OverwriteExisting=*/true);
+ getStreamer().changeISAMappingSymbol(Attribute, String);
}
void RISCVTargetELFStreamer::emitIntTextAttribute(unsigned Attribute,
@@ -147,7 +148,10 @@ void RISCVELFStreamer::emitDataMappingSymbol() {
void RISCVELFStreamer::emitInstructionsMappingSymbol() {
if (LastEMS == EMS_Instructions)
return;
- emitMappingSymbol("$x");
+ if (LastEMS == EMS_ChangeISA)
+ emitMappingSymbol("$x" + ISAString);
+ else
+ emitMappingSymbol("$x");
LastEMS = EMS_Instructions;
}
@@ -159,6 +163,16 @@ void RISCVELFStreamer::emitMappingSymbol(StringRef Name) {
Symbol->setBinding(ELF::STB_LOCAL);
}
+void RISCVELFStreamer::changeISAMappingSymbol(unsigned Attribute,
+ StringRef arch) {
+ if (Attribute != RISCVAttrs::ARCH)
+ return;
+ if (arch != ISAString) {
+ LastEMS = EMS_ChangeISA;
+ ISAString = std::string(arch);
+ }
+}
+
void RISCVELFStreamer::changeSection(MCSection *Section,
const MCExpr *Subsection) {
// We have to keep track of the mapping symbol state of any sections we
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index a6f54bf67b5d2b..88fb5b235388ef 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -20,11 +20,13 @@ class RISCVELFStreamer : public MCELFStreamer {
void emitInstructionsMappingSymbol();
void emitMappingSymbol(StringRef Name);
- enum ElfMappingSymbol { EMS_None, EMS_Instructions, EMS_Data };
+ enum ElfMappingSymbol { EMS_None, EMS_ChangeISA, EMS_Instructions,
+ EMS_Data };
int64_t MappingSymbolCounter = 0;
DenseMap<const MCSection *, ElfMappingSymbol> LastMappingSymbols;
ElfMappingSymbol LastEMS = EMS_None;
+ std::string ISAString;
public:
RISCVELFStreamer(MCContext &C, std::unique_ptr<MCAsmBackend> MAB,
@@ -37,6 +39,7 @@ class RISCVELFStreamer : public MCELFStreamer {
void emitBytes(StringRef Data) override;
void emitFill(const MCExpr &NumBytes, uint64_t FillValue, SMLoc Loc) override;
void emitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) override;
+ void changeISAMappingSymbol(unsigned Attribute, StringRef arch);
};
namespace llvm {
diff --git a/llvm/test/MC/RISCV/mapping-isa.s b/llvm/test/MC/RISCV/mapping-isa.s
new file mode 100644
index 00000000000000..737746e889ffb5
--- /dev/null
+++ b/llvm/test/MC/RISCV/mapping-isa.s
@@ -0,0 +1,47 @@
+## Instruction mapping symbols with ISA string
+
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -o %t.o %s
+# RUN: llvm-objdump -t %t.o | FileCheck %s -check-prefix=CHECK-MAPPINGSYMBOLS
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -o %t.o %s
+# RUN: llvm-objdump -t %t.o | FileCheck %s -check-prefix=CHECK-MAPPINGSYMBOLS
+
+.text
+.attribute arch, "rv32i"
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv32i2p1
+
+.attribute arch, "rv32i"
+nop
+nop
+# CHECK-MAPPINGSYMBOLS-NOT: $xrv32i2p1
+## Multiple instructions with same isa string, so no mapping symbol expected.
+
+.word 4
+nop
+# CHECK-MAPPINGSYMBOLS-NOT: $xrv32i2p1
+# CHECK-MAPPINGSYMBOLS: $x
+## Data followed by an instruction should produce an instruction mapping
+## symbol, but the isa string should not be present.
+
+.attribute arch, "rv32i2p1"
+nop
+# CHECK-MAPPINGSYMBOLS-NOT: $xrv32i2p1
+## The arch "rv32i" and "rv32i2p1" has the same isa string, so no mapping
+## symbol expected.
+
+.attribute arch, "rv32e"
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv32e2p0
+
+.attribute arch, "rv64e"
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv64e2p0
+
+.attribute arch, "rv32g"
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0
+
+.attribute arch, "rv64g"
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv64i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0
+
>From 2254e3c572476f7324745e531ed5539efc83b5bf Mon Sep 17 00:00:00 2001
From: "Joseph.Faulls" <Joseph.Faulls at imgtec.com>
Date: Thu, 28 Sep 2023 17:06:02 +0100
Subject: [PATCH 2/7] Fix formatting
---
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index 88fb5b235388ef..46b56298b7885f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -20,8 +20,7 @@ class RISCVELFStreamer : public MCELFStreamer {
void emitInstructionsMappingSymbol();
void emitMappingSymbol(StringRef Name);
- enum ElfMappingSymbol { EMS_None, EMS_ChangeISA, EMS_Instructions,
- EMS_Data };
+ enum ElfMappingSymbol { EMS_None, EMS_ChangeISA, EMS_Instructions, EMS_Data };
int64_t MappingSymbolCounter = 0;
DenseMap<const MCSection *, ElfMappingSymbol> LastMappingSymbols;
>From f7a10a765f8f531f2375aaddf7379a2d9c3cfe2d Mon Sep 17 00:00:00 2001
From: "Joseph.Faulls" <Joseph.Faulls at imgtec.com>
Date: Mon, 16 Oct 2023 16:20:08 +0100
Subject: [PATCH 3/7] Add support for .option assembler directive
---
.../RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 110 +++++++++++++++---
.../RISCV/MCTargetDesc/RISCVELFStreamer.h | 11 +-
...{mapping-isa.s => mapping-isa-attribute.s} | 15 ++-
llvm/test/MC/RISCV/mapping-isa-option-rv32.s | 36 ++++++
llvm/test/MC/RISCV/mapping-isa-option-rv64.s | 36 ++++++
5 files changed, 183 insertions(+), 25 deletions(-)
rename llvm/test/MC/RISCV/{mapping-isa.s => mapping-isa-attribute.s} (72%)
create mode 100644 llvm/test/MC/RISCV/mapping-isa-option-rv32.s
create mode 100644 llvm/test/MC/RISCV/mapping-isa-option-rv64.s
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index f5fd814eefad37..e8b21837d530a4 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -25,6 +25,7 @@
#include "llvm/MC/MCValue.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/RISCVAttributes.h"
+#include <sstream>
using namespace llvm;
@@ -44,14 +45,33 @@ RISCVTargetELFStreamer::RISCVTargetELFStreamer(MCStreamer &S,
// its ParseInstruction may call setForceRelocs as well.
if (STI.hasFeature(RISCV::FeatureRelax))
static_cast<RISCVAsmBackend &>(MAB).setForceRelocs();
+
+ // Using RISCVISAInfo, construct ISAString from given features.
+ std::stringstream SS(STI.getFeatureString().str());
+ std::string Feature;
+ std::vector<std::string> FeatureVec;
+ while (std::getline(SS, Feature, ','))
+ FeatureVec.push_back(Feature);
+
+ auto ParseResult = RISCVISAInfo::parseFeatures(
+ STI.getTargetTriple().isRISCV64() ? 64 : 32, FeatureVec);
+ if (ParseResult) {
+ auto &ISAInfo = *ParseResult;
+ ISAString = ISAInfo->toString();
+ }
}
RISCVELFStreamer &RISCVTargetELFStreamer::getStreamer() {
return static_cast<RISCVELFStreamer &>(Streamer);
}
-void RISCVTargetELFStreamer::emitDirectiveOptionPush() {}
-void RISCVTargetELFStreamer::emitDirectiveOptionPop() {}
+void RISCVTargetELFStreamer::setArchString(StringRef Arch) {
+ if (Arch != ISAString) {
+ getStreamer().setNewISAString(Arch);
+ ISAString = Arch;
+ }
+}
+
void RISCVTargetELFStreamer::emitDirectiveOptionPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
@@ -66,7 +86,69 @@ void RISCVTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
void RISCVTargetELFStreamer::emitTextAttribute(unsigned Attribute,
StringRef String) {
getStreamer().setAttributeItem(Attribute, String, /*OverwriteExisting=*/true);
- getStreamer().changeISAMappingSymbol(Attribute, String);
+ if (Attribute == RISCVAttrs::ARCH)
+ setArchString(String);
+}
+
+void RISCVTargetELFStreamer::emitDirectiveOptionArch(
+ ArrayRef<RISCVOptionArchArg> Args) {
+ if (Args.size() == 1) {
+ RISCVOptionArchArg Arg = Args[0];
+ if (Arg.Type == RISCVOptionArchArgType::Full) {
+ // If there is a full arch string, then just set the arch string and
+ // return. It is illegal to have more than one argument with this option.
+ setArchString(Arg.Value);
+ return;
+ }
+ }
+
+ auto ParseResult = RISCVISAInfo::parseArchString(ISAString, false);
+ if (!ParseResult) {
+ std::string Buffer;
+ raw_string_ostream OutputErrMsg(Buffer);
+ handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+ OutputErrMsg << "invalid arch name '" << ISAString << "', "
+ << ErrMsg.getMessage();
+ });
+ return;
+ }
+ auto &ISAInfo = *ParseResult;
+ std::vector<std::string> NewFeatures = ISAInfo->toFeatureVector();
+ for (RISCVOptionArchArg Arg : Args) {
+ switch (Arg.Type) {
+ case RISCVOptionArchArgType::Minus:
+ NewFeatures.push_back("-" + Arg.Value);
+ break;
+ case RISCVOptionArchArgType::Plus:
+ NewFeatures.push_back("+" + Arg.Value);
+ break;
+ case RISCVOptionArchArgType::Full:
+ // This is special cased at the beginning of this function.
+ // It is illegal to have more than one argument for this option.
+ llvm_unreachable("Improperly formed arch option");
+ break;
+ }
+ }
+ auto NewParseResult = RISCVISAInfo::parseFeatures(
+ STI.hasFeature(RISCV::Feature64Bit) ? 64 : 32, NewFeatures);
+ if (!NewParseResult) {
+ std::string Buffer;
+ raw_string_ostream OutputErrMsg(Buffer);
+ handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
+ OutputErrMsg << "Bad set of features. " << ErrMsg.getMessage();
+ });
+ return;
+ }
+ auto &NewISAInfo = *NewParseResult;
+ setArchString(NewISAInfo->toString());
+}
+
+void RISCVTargetELFStreamer::emitDirectiveOptionPush() {
+ ISAStringStack.push_back(ISAString);
+}
+
+void RISCVTargetELFStreamer::emitDirectiveOptionPop() {
+ setArchString(ISAStringStack.pop_back_val());
}
void RISCVTargetELFStreamer::emitIntTextAttribute(unsigned Attribute,
@@ -146,12 +228,14 @@ void RISCVELFStreamer::emitDataMappingSymbol() {
}
void RISCVELFStreamer::emitInstructionsMappingSymbol() {
- if (LastEMS == EMS_Instructions)
- return;
- if (LastEMS == EMS_ChangeISA)
- emitMappingSymbol("$x" + ISAString);
- else
+ // If NewISAString string has a value, this means there has been a change
+ // of ISA, so emit an ISA mapping symbol.
+ if (!NewISAString.empty()) {
+ emitMappingSymbol("$x" + NewISAString);
+ NewISAString.clear();
+ } else if (LastEMS != EMS_Instructions) {
emitMappingSymbol("$x");
+ }
LastEMS = EMS_Instructions;
}
@@ -163,14 +247,8 @@ void RISCVELFStreamer::emitMappingSymbol(StringRef Name) {
Symbol->setBinding(ELF::STB_LOCAL);
}
-void RISCVELFStreamer::changeISAMappingSymbol(unsigned Attribute,
- StringRef arch) {
- if (Attribute != RISCVAttrs::ARCH)
- return;
- if (arch != ISAString) {
- LastEMS = EMS_ChangeISA;
- ISAString = std::string(arch);
- }
+void RISCVELFStreamer::setNewISAString(StringRef Arch) {
+ NewISAString = std::string(Arch);
}
void RISCVELFStreamer::changeSection(MCSection *Section,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index 46b56298b7885f..d8f0e555302914 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -20,12 +20,12 @@ class RISCVELFStreamer : public MCELFStreamer {
void emitInstructionsMappingSymbol();
void emitMappingSymbol(StringRef Name);
- enum ElfMappingSymbol { EMS_None, EMS_ChangeISA, EMS_Instructions, EMS_Data };
+ enum ElfMappingSymbol { EMS_None, EMS_Instructions, EMS_Data };
int64_t MappingSymbolCounter = 0;
DenseMap<const MCSection *, ElfMappingSymbol> LastMappingSymbols;
ElfMappingSymbol LastEMS = EMS_None;
- std::string ISAString;
+ std::string NewISAString;
public:
RISCVELFStreamer(MCContext &C, std::unique_ptr<MCAsmBackend> MAB,
@@ -38,7 +38,7 @@ class RISCVELFStreamer : public MCELFStreamer {
void emitBytes(StringRef Data) override;
void emitFill(const MCExpr &NumBytes, uint64_t FillValue, SMLoc Loc) override;
void emitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) override;
- void changeISAMappingSymbol(unsigned Attribute, StringRef arch);
+ void setNewISAString(StringRef Arch);
};
namespace llvm {
@@ -46,6 +46,8 @@ namespace llvm {
class RISCVTargetELFStreamer : public RISCVTargetStreamer {
private:
StringRef CurrentVendor;
+ std::string ISAString;
+ SmallVector<std::string, 4> ISAStringStack;
MCSection *AttributeSection = nullptr;
const MCSubtargetInfo &STI;
@@ -71,6 +73,9 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
+ void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
+
+ void setArchString(StringRef Arch);
void finish() override;
};
diff --git a/llvm/test/MC/RISCV/mapping-isa.s b/llvm/test/MC/RISCV/mapping-isa-attribute.s
similarity index 72%
rename from llvm/test/MC/RISCV/mapping-isa.s
rename to llvm/test/MC/RISCV/mapping-isa-attribute.s
index 737746e889ffb5..0b942f0c87c035 100644
--- a/llvm/test/MC/RISCV/mapping-isa.s
+++ b/llvm/test/MC/RISCV/mapping-isa-attribute.s
@@ -1,13 +1,17 @@
## Instruction mapping symbols with ISA string
-# RUN: llvm-mc -triple=riscv32 -filetype=obj -o %t.o %s
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+c -o %t.o %s
# RUN: llvm-objdump -t %t.o | FileCheck %s -check-prefix=CHECK-MAPPINGSYMBOLS
-# RUN: llvm-mc -triple=riscv64 -filetype=obj -o %t.o %s
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+c -o %t.o %s
# RUN: llvm-objdump -t %t.o | FileCheck %s -check-prefix=CHECK-MAPPINGSYMBOLS
.text
-.attribute arch, "rv32i"
+.attribute arch, "rv32ic"
nop
+# CHECK-MAPPINGSYMBOLS-NOT: $xrv32i2p1_c2p0
+# No mapping symbol as arch has not changed given the attributes
+
+.attribute arch, "rv32i"
# CHECK-MAPPINGSYMBOLS: $xrv32i2p1
.attribute arch, "rv32i"
@@ -25,8 +29,8 @@ nop
.attribute arch, "rv32i2p1"
nop
-# CHECK-MAPPINGSYMBOLS-NOT: $xrv32i2p1
-## The arch "rv32i" and "rv32i2p1" has the same isa string, so no mapping
+# CHECK-MAPPINGSYMBOLS-NOT: $xrv32i2p0
+## The arch "rv32ic" and "rv32i2p1" has the same isa string, so no mapping
## symbol expected.
.attribute arch, "rv32e"
@@ -44,4 +48,3 @@ nop
.attribute arch, "rv64g"
nop
# CHECK-MAPPINGSYMBOLS: $xrv64i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0
-
diff --git a/llvm/test/MC/RISCV/mapping-isa-option-rv32.s b/llvm/test/MC/RISCV/mapping-isa-option-rv32.s
new file mode 100644
index 00000000000000..0815c7c5bf029d
--- /dev/null
+++ b/llvm/test/MC/RISCV/mapping-isa-option-rv32.s
@@ -0,0 +1,36 @@
+## Instruction mapping symbols with ISA string
+
+# RUN: llvm-mc -triple=riscv32 -mattr=+f,+a -filetype=obj -o %t.o %s
+# RUN: llvm-objdump -t %t.o | FileCheck %s -check-prefix=CHECK-MAPPINGSYMBOLS
+
+.text
+nop
+# CHECK-MAPPINGSYMBOLS-NOT: $xrv32
+
+.option push
+.option arch, -f
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv32i2p1_a2p1_zicsr2p0
+
+.option pop
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv32i2p1_a2p1_f2p2_zicsr2p0
+
+.option push
+.option arch, +c
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv32i2p1_a2p1_f2p2_c2p0_zicsr2p0
+
+.option pop
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv32i2p1_a2p1_f2p2_zicsr2p0
+
+.option arch, rv32imac
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv32i2p1_m2p0_a2p1_c2p0
+nop
+# CHECK-MAPPINGSYMBOLS-NOT: $xrv32i2p1_m2p0_a2p1_c2p0
+
+.word 4
+nop
+# CHECK-MAPPINGSYMBOLS-NOT: $xrv32i2p1_m2p0_a2p1_c2p0
diff --git a/llvm/test/MC/RISCV/mapping-isa-option-rv64.s b/llvm/test/MC/RISCV/mapping-isa-option-rv64.s
new file mode 100644
index 00000000000000..3d3ab9384dda65
--- /dev/null
+++ b/llvm/test/MC/RISCV/mapping-isa-option-rv64.s
@@ -0,0 +1,36 @@
+## Instruction mapping symbols with ISA string
+
+# RUN: llvm-mc -triple=riscv64 -mattr=+f,+a -filetype=obj -o %t.o %s
+# RUN: llvm-objdump -t %t.o | FileCheck %s -check-prefix=CHECK-MAPPINGSYMBOLS
+
+.text
+nop
+# CHECK-MAPPINGSYMBOLS-NOT: $xrv64
+
+.option push
+.option arch, -f
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv64i2p1_a2p1_zicsr2p0
+
+.option pop
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv64i2p1_a2p1_f2p2_zicsr2p0
+
+.option push
+.option arch, +c
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv64i2p1_a2p1_f2p2_c2p0_zicsr2p0
+
+.option pop
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv64i2p1_a2p1_f2p2_zicsr2p0
+
+.option arch, rv64imac
+nop
+# CHECK-MAPPINGSYMBOLS: $xrv64i2p1_m2p0_a2p1_c2p0
+nop
+# CHECK-MAPPINGSYMBOLS-NOT: $xrv64i2p1_m2p0_a2p1_c2p0
+
+.word 4
+nop
+# CHECK-MAPPINGSYMBOLS-NOT: $xrv64i2p1_m2p0_a2p1_c2p0
>From 5f25e4110569846c1e32468c019ba6692700446f Mon Sep 17 00:00:00 2001
From: "Joseph.Faulls" <Joseph.Faulls at imgtec.com>
Date: Thu, 11 Jan 2024 11:13:04 +0000
Subject: [PATCH 4/7] Fix build error
---
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index e8b21837d530a4..510671b4f23945 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -113,7 +113,7 @@ void RISCVTargetELFStreamer::emitDirectiveOptionArch(
return;
}
auto &ISAInfo = *ParseResult;
- std::vector<std::string> NewFeatures = ISAInfo->toFeatureVector();
+ std::vector<std::string> NewFeatures = ISAInfo->toFeatures();
for (RISCVOptionArchArg Arg : Args) {
switch (Arg.Type) {
case RISCVOptionArchArgType::Minus:
>From 2b7d83f4a5a1b515ed577dccacf7e36d7d99af7d Mon Sep 17 00:00:00 2001
From: "Joseph.Faulls" <Joseph.Faulls at imgtec.com>
Date: Fri, 12 Jan 2024 10:49:22 +0000
Subject: [PATCH 5/7] Address review comments
---
.../RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 15 +++++++--------
.../Target/RISCV/MCTargetDesc/RISCVELFStreamer.h | 3 ++-
.../RISCV/MCTargetDesc/RISCVTargetStreamer.cpp | 4 ++--
.../RISCV/MCTargetDesc/RISCVTargetStreamer.h | 6 ++++--
4 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index 510671b4f23945..d4b7c16c558325 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -47,11 +47,11 @@ RISCVTargetELFStreamer::RISCVTargetELFStreamer(MCStreamer &S,
static_cast<RISCVAsmBackend &>(MAB).setForceRelocs();
// Using RISCVISAInfo, construct ISAString from given features.
- std::stringstream SS(STI.getFeatureString().str());
- std::string Feature;
- std::vector<std::string> FeatureVec;
- while (std::getline(SS, Feature, ','))
- FeatureVec.push_back(Feature);
+ SmallVector<StringRef, 8> FeatureSmallVec;
+ STI.getFeatureString().split(FeatureSmallVec, ',', /*MaxSplit*/ -1,
+ /*KeepEmpty*/ false);
+ std::vector<std::string> FeatureVec(FeatureSmallVec.begin(),
+ FeatureSmallVec.end());
auto ParseResult = RISCVISAInfo::parseFeatures(
STI.getTargetTriple().isRISCV64() ? 64 : 32, FeatureVec);
@@ -91,7 +91,7 @@ void RISCVTargetELFStreamer::emitTextAttribute(unsigned Attribute,
}
void RISCVTargetELFStreamer::emitDirectiveOptionArch(
- ArrayRef<RISCVOptionArchArg> Args) {
+ const ArrayRef<RISCVOptionArchArg> &Args) {
if (Args.size() == 1) {
RISCVOptionArchArg Arg = Args[0];
if (Arg.Type == RISCVOptionArchArgType::Full) {
@@ -114,7 +114,7 @@ void RISCVTargetELFStreamer::emitDirectiveOptionArch(
}
auto &ISAInfo = *ParseResult;
std::vector<std::string> NewFeatures = ISAInfo->toFeatures();
- for (RISCVOptionArchArg Arg : Args) {
+ for (const RISCVOptionArchArg &Arg : Args) {
switch (Arg.Type) {
case RISCVOptionArchArgType::Minus:
NewFeatures.push_back("-" + Arg.Value);
@@ -126,7 +126,6 @@ void RISCVTargetELFStreamer::emitDirectiveOptionArch(
// This is special cased at the beginning of this function.
// It is illegal to have more than one argument for this option.
llvm_unreachable("Improperly formed arch option");
- break;
}
}
auto NewParseResult = RISCVISAInfo::parseFeatures(
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index d8f0e555302914..d70aeabf078c63 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -73,7 +73,8 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
- void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
+ void
+ emitDirectiveOptionArch(const ArrayRef<RISCVOptionArchArg> &Args) override;
void setArchString(StringRef Arch);
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 29ffc3224b525b..a8f95ac6fc850f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -34,7 +34,7 @@ void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionArch(
- ArrayRef<RISCVOptionArchArg> Args) {}
+ const ArrayRef<RISCVOptionArchArg> &Args) {}
void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {}
void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
void RISCVTargetStreamer::finishAttributeSection() {}
@@ -104,7 +104,7 @@ void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
}
void RISCVTargetAsmStreamer::emitDirectiveOptionArch(
- ArrayRef<RISCVOptionArchArg> Args) {
+ const ArrayRef<RISCVOptionArchArg> &Args) {
OS << "\t.option\tarch";
for (const auto &Arg : Args) {
OS << ", ";
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
index 070e72fb157ae9..ee899a76c36e08 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -47,7 +47,8 @@ class RISCVTargetStreamer : public MCTargetStreamer {
virtual void emitDirectiveOptionNoRVC();
virtual void emitDirectiveOptionRelax();
virtual void emitDirectiveOptionNoRelax();
- virtual void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args);
+ virtual void
+ emitDirectiveOptionArch(const ArrayRef<RISCVOptionArchArg> &Args);
virtual void emitDirectiveVariantCC(MCSymbol &Symbol);
virtual void emitAttribute(unsigned Attribute, unsigned Value);
virtual void finishAttributeSection();
@@ -81,7 +82,8 @@ class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoRVC() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
- void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
+ void
+ emitDirectiveOptionArch(const ArrayRef<RISCVOptionArchArg> &Args) override;
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
};
>From 544c66192adc33d98a369913499b3ef1dcf356d5 Mon Sep 17 00:00:00 2001
From: "Joseph.Faulls" <Joseph.Faulls at imgtec.com>
Date: Fri, 12 Jan 2024 11:14:14 +0000
Subject: [PATCH 6/7] Remove unneeded include and fix formatting
---
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index d4b7c16c558325..a70985b22c15d2 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -25,7 +25,6 @@
#include "llvm/MC/MCValue.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/RISCVAttributes.h"
-#include <sstream>
using namespace llvm;
@@ -91,7 +90,7 @@ void RISCVTargetELFStreamer::emitTextAttribute(unsigned Attribute,
}
void RISCVTargetELFStreamer::emitDirectiveOptionArch(
- const ArrayRef<RISCVOptionArchArg> &Args) {
+ const ArrayRef<RISCVOptionArchArg> &Args) {
if (Args.size() == 1) {
RISCVOptionArchArg Arg = Args[0];
if (Arg.Type == RISCVOptionArchArgType::Full) {
>From 643b88fbbd88ecfcbe91acd26684536b0972c16d Mon Sep 17 00:00:00 2001
From: "Joseph.Faulls" <Joseph.Faulls at imgtec.com>
Date: Mon, 26 Feb 2024 11:52:46 +0000
Subject: [PATCH 7/7] Use parseFeatureBits over parseFeatures and revert const
reference arg
---
.../Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 13 +++----------
.../Target/RISCV/MCTargetDesc/RISCVELFStreamer.h | 3 +--
.../RISCV/MCTargetDesc/RISCVTargetStreamer.cpp | 4 ++--
.../Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h | 6 ++----
4 files changed, 8 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index a70985b22c15d2..dd7f8fd606e6bd 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -45,15 +45,8 @@ RISCVTargetELFStreamer::RISCVTargetELFStreamer(MCStreamer &S,
if (STI.hasFeature(RISCV::FeatureRelax))
static_cast<RISCVAsmBackend &>(MAB).setForceRelocs();
- // Using RISCVISAInfo, construct ISAString from given features.
- SmallVector<StringRef, 8> FeatureSmallVec;
- STI.getFeatureString().split(FeatureSmallVec, ',', /*MaxSplit*/ -1,
- /*KeepEmpty*/ false);
- std::vector<std::string> FeatureVec(FeatureSmallVec.begin(),
- FeatureSmallVec.end());
-
- auto ParseResult = RISCVISAInfo::parseFeatures(
- STI.getTargetTriple().isRISCV64() ? 64 : 32, FeatureVec);
+ auto ParseResult = RISCVFeatures::parseFeatureBits(
+ STI.getTargetTriple().isRISCV64(), Features);
if (ParseResult) {
auto &ISAInfo = *ParseResult;
ISAString = ISAInfo->toString();
@@ -90,7 +83,7 @@ void RISCVTargetELFStreamer::emitTextAttribute(unsigned Attribute,
}
void RISCVTargetELFStreamer::emitDirectiveOptionArch(
- const ArrayRef<RISCVOptionArchArg> &Args) {
+ ArrayRef<RISCVOptionArchArg> Args) {
if (Args.size() == 1) {
RISCVOptionArchArg Arg = Args[0];
if (Arg.Type == RISCVOptionArchArgType::Full) {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index d70aeabf078c63..d8f0e555302914 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -73,8 +73,7 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
- void
- emitDirectiveOptionArch(const ArrayRef<RISCVOptionArchArg> &Args) override;
+ void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
void setArchString(StringRef Arch);
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index a8f95ac6fc850f..29ffc3224b525b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -34,7 +34,7 @@ void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionArch(
- const ArrayRef<RISCVOptionArchArg> &Args) {}
+ ArrayRef<RISCVOptionArchArg> Args) {}
void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {}
void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
void RISCVTargetStreamer::finishAttributeSection() {}
@@ -104,7 +104,7 @@ void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
}
void RISCVTargetAsmStreamer::emitDirectiveOptionArch(
- const ArrayRef<RISCVOptionArchArg> &Args) {
+ ArrayRef<RISCVOptionArchArg> Args) {
OS << "\t.option\tarch";
for (const auto &Arg : Args) {
OS << ", ";
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
index ee899a76c36e08..070e72fb157ae9 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -47,8 +47,7 @@ class RISCVTargetStreamer : public MCTargetStreamer {
virtual void emitDirectiveOptionNoRVC();
virtual void emitDirectiveOptionRelax();
virtual void emitDirectiveOptionNoRelax();
- virtual void
- emitDirectiveOptionArch(const ArrayRef<RISCVOptionArchArg> &Args);
+ virtual void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args);
virtual void emitDirectiveVariantCC(MCSymbol &Symbol);
virtual void emitAttribute(unsigned Attribute, unsigned Value);
virtual void finishAttributeSection();
@@ -82,8 +81,7 @@ class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoRVC() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
- void
- emitDirectiveOptionArch(const ArrayRef<RISCVOptionArchArg> &Args) override;
+ void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
};
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