[llvm] [AArch64][GlobalISel] Legalize Insert vector element (PR #81453)

[David Green via llvm-commits]

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@@ -2121,6 +2120,36 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) {
     }
     return false;
   }
+  case TargetOpcode::G_INSERT_VECTOR_ELT: {
+    // The tablegen patterns for integer insert_vector_elts with small elements
+    // will expect the operand to be legalized to a i32 type. This extends the
+    // types of i8 and i16 element inserts, so that the existing tablegen
+    // patterns can apply.
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davemgreen wrote:

I think this needs to be after reg-bank selection. Otherwise there isn't a good way to detect INSERT_VECTOR_ELT from gpr values vs fpr registers for the same type size.
The process is irtranslation -> opt -> legalization -> opt -> regbank select -> regbank-dependant legalization -> selection. And currently that lives in this preISelLower method. I'm not sure if it's the best place for it, but there are other operations like select that could do with post-reg-back-select legalization to treat grp selects differently to fpr.

https://github.com/llvm/llvm-project/pull/81453