[llvm] [RISCV] Fix insert_subvector with fixed vector type creating invalid node (PR #82975)

[Luke Lau via llvm-commits]

https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/82975

If the vector type is a fixed vector type, we convert it to a container
scalable vector type to compute its reg class. But we need to keep the old
fixed type so we create a result node with the same type.

This code path is currently dead so I haven't been able to create a test case
for it. But I have an upcoming patch for insert_subvector lowering that will
exercise this.


>From 1e3d7b13411620131afbcf9e9d17d9c5f8d9a466 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 26 Feb 2024 17:43:15 +0800
Subject: [PATCH] [RISCV] Fix insert_subvector with fixed vector type creating
 invalid node

If the vector type is a fixed vector type, we convert it to a container
scalable vector type to compute its reg class. But we need to keep the old
fixed type so we create a result node with the same type.

This code path is currently dead so I haven't been able to create a test case
for it. But I have an upcoming patch for insert_subvector lowering that will
exercise this.
---
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index c922098c55094e..1b8c1434c9f2d9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2066,14 +2066,15 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       assert(Idx == 0 && V.isUndef());
       SubVecContainerVT = TLI.getContainerForFixedLengthVector(SubVecVT);
     }
+    MVT ContainerVT = VT;
     if (VT.isFixedLengthVector())
-      VT = TLI.getContainerForFixedLengthVector(VT);
+      ContainerVT = TLI.getContainerForFixedLengthVector(VT);
 
     const auto *TRI = Subtarget->getRegisterInfo();
     unsigned SubRegIdx;
     std::tie(SubRegIdx, Idx) =
         RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(
-            VT, SubVecContainerVT, Idx, TRI);
+            ContainerVT, SubVecContainerVT, Idx, TRI);
 
     // If the Idx hasn't been completely eliminated then this is a subvector
     // insert which doesn't naturally align to a vector register. These must
@@ -2093,7 +2094,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     // If we haven't set a SubRegIdx, then we must be going between
     // equally-sized LMUL groups (e.g. VR -> VR). This can be done as a copy.
     if (SubRegIdx == RISCV::NoSubRegister) {
-      unsigned InRegClassID = RISCVTargetLowering::getRegClassIDForVecVT(VT);
+      unsigned InRegClassID =
+          RISCVTargetLowering::getRegClassIDForVecVT(ContainerVT);
       assert(RISCVTargetLowering::getRegClassIDForVecVT(SubVecContainerVT) ==
                  InRegClassID &&
              "Unexpected subvector extraction");