[llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)

[Wang Pengcheng via llvm-commits]

================
@@ -105,22 +105,66 @@ defm AMOMAXU_D  : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">,
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
+// An atomic load operation that does not need either acquire or release
+// semantics.
+class relaxed_load<PatFrags base>
+  : PatFrag<(ops node:$ptr), (base node:$ptr)> {
+  let IsAtomic = 1;
----------------
wangpc-pp wrote:

Yes, I know it (I referred to AArhc64 too). :-)
I meant that we can reduce some lines via using above approaches.

https://github.com/llvm/llvm-project/pull/82914