[llvm] 767433b - [AMDGPU] fixes duplicate expressions in if stmnts in SIISelLowering.cpp (#82018)
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Sun Feb 18 07:49:18 PST 2024
Author: Nick Anderson
Date: 2024-02-18T21:19:15+05:30
New Revision: 767433ba88212b70da51ddc41727624c790cc329
URL: https://github.com/llvm/llvm-project/commit/767433ba88212b70da51ddc41727624c790cc329
DIFF: https://github.com/llvm/llvm-project/commit/767433ba88212b70da51ddc41727624c790cc329.diff
LOG: [AMDGPU] fixes duplicate expressions in if stmnts in SIISelLowering.cpp (#82018)
fixes #81766
Added:
Modified:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 7be670f8e76c37..5e1d7508503741 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -6306,7 +6306,7 @@ SDValue SITargetLowering::lowerFMINNUM_FMAXNUM(SDValue Op,
return expandFMINNUM_FMAXNUM(Op.getNode(), DAG);
if (VT == MVT::v4f16 || VT == MVT::v8f16 || VT == MVT::v16f16 ||
- VT == MVT::v16f16)
+ VT == MVT::v32f16)
return splitBinaryVectorOp(Op, DAG);
return Op;
}
@@ -14571,7 +14571,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
EVT VT = N->getValueType(0);
// v2i16 (scalar_to_vector i16:x) -> v2i16 (bitcast (any_extend i16:x))
- if (VT == MVT::v2i16 || VT == MVT::v2f16 || VT == MVT::v2f16) {
+ if (VT == MVT::v2i16 || VT == MVT::v2f16 || VT == MVT::v2bf16) {
SDLoc SL(N);
SDValue Src = N->getOperand(0);
EVT EltVT = Src.getValueType();
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