[llvm] 1e4c76c - [MC][AsmParser] Make `MatchRegisterName` return `MCRegister` (NFC) (#81408)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 18 02:59:53 PST 2024
Author: Sergei Barannikov
Date: 2024-02-18T13:59:49+03:00
New Revision: 1e4c76cdc9d47c06eb30c811fd497d7b0a3ae5e8
URL: https://github.com/llvm/llvm-project/commit/1e4c76cdc9d47c06eb30c811fd497d7b0a3ae5e8
DIFF: https://github.com/llvm/llvm-project/commit/1e4c76cdc9d47c06eb30c811fd497d7b0a3ae5e8.diff
LOG: [MC][AsmParser] Make `MatchRegisterName` return `MCRegister` (NFC) (#81408)
`MCRegister` is preferred over `unsigned` nowadays.
Added:
Modified:
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
llvm/test/TableGen/AllowDuplicateRegisterNames.td
llvm/utils/TableGen/AsmMatcherEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 4e7c8f66d9d549..db847e640b7cdd 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2600,7 +2600,7 @@ void AArch64Operand::print(raw_ostream &OS) const {
/// @name Auto-generated Match Functions
/// {
-static unsigned MatchRegisterName(StringRef Name);
+static MCRegister MatchRegisterName(StringRef Name);
/// }
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index e534f1f7146dcc..c82ab57bdf80f1 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -4045,7 +4045,7 @@ void ARMOperand::print(raw_ostream &OS) const {
/// @name Auto-generated Match Functions
/// {
-static unsigned MatchRegisterName(StringRef Name);
+static MCRegister MatchRegisterName(StringRef Name);
/// }
diff --git a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
index bb9710d13a9d93..db4aa03437c648 100644
--- a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
+++ b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
@@ -68,7 +68,7 @@ class AVRAsmParser : public MCTargetAsmParser {
ParseStatus parseMemriOperand(OperandVector &Operands);
bool parseOperand(OperandVector &Operands, bool maybeReg);
- int parseRegisterName(unsigned (*matchFn)(StringRef));
+ int parseRegisterName(MCRegister (*matchFn)(StringRef));
int parseRegisterName();
int parseRegister(bool RestoreOnFailure = false);
bool tryParseRegisterOperand(OperandVector &Operands);
@@ -276,11 +276,11 @@ class AVROperand : public MCParsedAsmOperand {
/// Maps from the set of all register names to a register number.
/// \note Generated by TableGen.
-static unsigned MatchRegisterName(StringRef Name);
+static MCRegister MatchRegisterName(StringRef Name);
/// Maps from the set of all alternative registernames to a register number.
/// \note Generated by TableGen.
-static unsigned MatchRegisterAltName(StringRef Name);
+static MCRegister MatchRegisterAltName(StringRef Name);
bool AVRAsmParser::invalidOperand(SMLoc const &Loc,
OperandVector const &Operands,
@@ -346,7 +346,7 @@ bool AVRAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
/// Parses a register name using a given matching function.
/// Checks for lowercase or uppercase if necessary.
-int AVRAsmParser::parseRegisterName(unsigned (*matchFn)(StringRef)) {
+int AVRAsmParser::parseRegisterName(MCRegister (*matchFn)(StringRef)) {
StringRef Name = Parser.getTok().getString();
int RegNum = matchFn(Name);
diff --git a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
index f875cee9a9b3ce..ff3649b77e351e 100644
--- a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
+++ b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
@@ -40,7 +40,7 @@
using namespace llvm;
// Auto-generated by TableGen
-static unsigned MatchRegisterName(StringRef Name);
+static MCRegister MatchRegisterName(StringRef Name);
namespace {
diff --git a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
index f3213ee72d9a69..818a468612a57e 100644
--- a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
+++ b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
@@ -286,8 +286,8 @@ bool MSP430AsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
}
// Auto-generated by TableGen
-static unsigned MatchRegisterName(StringRef Name);
-static unsigned MatchRegisterAltName(StringRef Name);
+static MCRegister MatchRegisterName(StringRef Name);
+static MCRegister MatchRegisterAltName(StringRef Name);
bool MSP430AsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) {
diff --git a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
index 21d5f7653a689b..f9e30a3a9378a9 100644
--- a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
+++ b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
@@ -56,7 +56,7 @@ class VEAsmParser : public MCTargetAsmParser {
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
- int parseRegisterName(unsigned (*matchFn)(StringRef));
+ int parseRegisterName(MCRegister (*matchFn)(StringRef));
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
@@ -805,7 +805,7 @@ bool VEAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
/// Parses a register name using a given matching function.
/// Checks for lowercase or uppercase if necessary.
-int VEAsmParser::parseRegisterName(unsigned (*matchFn)(StringRef)) {
+int VEAsmParser::parseRegisterName(MCRegister (*matchFn)(StringRef)) {
StringRef Name = Parser.getTok().getString();
int RegNum = matchFn(Name);
@@ -821,11 +821,11 @@ int VEAsmParser::parseRegisterName(unsigned (*matchFn)(StringRef)) {
/// Maps from the set of all register names to a register number.
/// \note Generated by TableGen.
-static unsigned MatchRegisterName(StringRef Name);
+static MCRegister MatchRegisterName(StringRef Name);
/// Maps from the set of all alternative registernames to a register number.
/// \note Generated by TableGen.
-static unsigned MatchRegisterAltName(StringRef Name);
+static MCRegister MatchRegisterAltName(StringRef Name);
ParseStatus VEAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) {
diff --git a/llvm/test/TableGen/AllowDuplicateRegisterNames.td b/llvm/test/TableGen/AllowDuplicateRegisterNames.td
index 897a628fe64b81..074e9847209af9 100644
--- a/llvm/test/TableGen/AllowDuplicateRegisterNames.td
+++ b/llvm/test/TableGen/AllowDuplicateRegisterNames.td
@@ -41,7 +41,7 @@ def GPR64 : RegisterClass<"Arch", [i64], 64, (add
(sequence "R%u_64", 0, 3)
)>;
-// CHECK: static unsigned MatchRegisterName(StringRef Name) {
+// CHECK: static MCRegister MatchRegisterName(StringRef Name) {
// CHECK: switch (Name.size()) {
// CHECK: default: break;
// CHECK: case 2: // 8 strings to match.
@@ -50,20 +50,20 @@ def GPR64 : RegisterClass<"Arch", [i64], 64, (add
// CHECK: switch (Name[1]) {
// CHECK: default: break;
// CHECK: case '0': // 2 strings to match.
-// CHECK: return 1; // "r0"
+// CHECK: return Arch::R0_32; // "r0"
// CHECK: case '1': // 2 strings to match.
-// CHECK: return 3; // "r1"
+// CHECK: return Arch::R1_32; // "r1"
// CHECK: case '2': // 2 strings to match.
-// CHECK: return 5; // "r2"
+// CHECK: return Arch::R2_32; // "r2"
// CHECK: case '3': // 2 strings to match.
-// CHECK: return 7; // "r3"
+// CHECK: return Arch::R3_32; // "r3"
// CHECK: }
// CHECK: break;
// CHECK: }
-// CHECK: return 0;
+// CHECK: return Arch::NoRegister;
// CHECK: }
-// CHECK: static unsigned MatchRegisterAltName(StringRef Name) {
+// CHECK: static MCRegister MatchRegisterAltName(StringRef Name) {
// CHECK: switch (Name.size()) {
// CHECK: default: break;
// CHECK: case 2: // 8 strings to match.
@@ -72,15 +72,15 @@ def GPR64 : RegisterClass<"Arch", [i64], 64, (add
// CHECK: switch (Name[1]) {
// CHECK: default: break;
// CHECK: case '0': // 2 strings to match.
-// CHECK: return 1; // "x0"
+// CHECK: return Arch::R0_32; // "x0"
// CHECK: case '1': // 2 strings to match.
-// CHECK: return 3; // "x1"
+// CHECK: return Arch::R1_32; // "x1"
// CHECK: case '2': // 2 strings to match.
-// CHECK: return 5; // "x2"
+// CHECK: return Arch::R2_32; // "x2"
// CHECK: case '3': // 2 strings to match.
-// CHECK: return 7; // "x3"
+// CHECK: return Arch::R3_32; // "x3"
// CHECK: }
// CHECK: break;
// CHECK: }
-// CHECK: return 0;
+// CHECK: return Arch::NoRegister;
// CHECK: }
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 3fcf2d87cc36ae..b5bd9bfd21bebc 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -2617,21 +2617,24 @@ static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
// Construct the match list.
std::vector<StringMatcher::StringPair> Matches;
const auto &Regs = Target.getRegBank().getRegisters();
+ std::string Namespace =
+ Regs.front().TheDef->getValueAsString("Namespace").str();
for (const CodeGenRegister &Reg : Regs) {
- if (Reg.TheDef->getValueAsString("AsmName").empty())
+ StringRef AsmName = Reg.TheDef->getValueAsString("AsmName");
+ if (AsmName.empty())
continue;
- Matches.emplace_back(std::string(Reg.TheDef->getValueAsString("AsmName")),
- "return " + utostr(Reg.EnumValue) + ";");
+ Matches.emplace_back(AsmName.str(), "return " + Namespace +
+ "::" + Reg.getName().str() + ';');
}
- OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
+ OS << "static MCRegister MatchRegisterName(StringRef Name) {\n";
bool IgnoreDuplicates =
AsmParser->getValueAsBit("AllowDuplicateRegisterNames");
StringMatcher("Name", Matches, OS).Emit(0, IgnoreDuplicates);
- OS << " return 0;\n";
+ OS << " return " << Namespace << "::NoRegister;\n";
OS << "}\n\n";
}
@@ -2642,6 +2645,8 @@ static void emitMatchRegisterAltName(CodeGenTarget &Target, Record *AsmParser,
// Construct the match list.
std::vector<StringMatcher::StringPair> Matches;
const auto &Regs = Target.getRegBank().getRegisters();
+ std::string Namespace =
+ Regs.front().TheDef->getValueAsString("Namespace").str();
for (const CodeGenRegister &Reg : Regs) {
auto AltNames = Reg.TheDef->getValueAsListOfStrings("AltNames");
@@ -2653,18 +2658,18 @@ static void emitMatchRegisterAltName(CodeGenTarget &Target, Record *AsmParser,
if (AltName.empty())
continue;
- Matches.emplace_back(std::string(AltName),
- "return " + utostr(Reg.EnumValue) + ";");
+ Matches.emplace_back(AltName.str(), "return " + Namespace +
+ "::" + Reg.getName().str() + ';');
}
}
- OS << "static unsigned MatchRegisterAltName(StringRef Name) {\n";
+ OS << "static MCRegister MatchRegisterAltName(StringRef Name) {\n";
bool IgnoreDuplicates =
AsmParser->getValueAsBit("AllowDuplicateRegisterNames");
StringMatcher("Name", Matches, OS).Emit(0, IgnoreDuplicates);
- OS << " return 0;\n";
+ OS << " return " << Namespace << "::NoRegister;\n";
OS << "}\n\n";
}
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