[llvm] [RISCV][ISel] Combine vector fadd/fsub/fmul with fp extend. (PR #81248)

[Wang Pengcheng via llvm-commits]

================
@@ -13656,24 +13723,30 @@ struct CombineResult {
 ///
 /// \returns std::nullopt if the pattern doesn't match or a CombineResult that
 /// can be used to apply the pattern.
-static std::optional<CombineResult>
-canFoldToVWWithSameExtensionImpl(SDNode *Root, const NodeExtensionHelper &LHS,
-                                 const NodeExtensionHelper &RHS, bool AllowSExt,
-                                 bool AllowZExt, SelectionDAG &DAG,
-                                 const RISCVSubtarget &Subtarget) {
-  assert((AllowSExt || AllowZExt) && "Forgot to set what you want?");
+static std::optional<CombineResult> canFoldToVWWithSameExtensionImpl(
+    SDNode *Root, const NodeExtensionHelper &LHS,
+    const NodeExtensionHelper &RHS, bool AllowSExt, bool AllowZExt,
+    bool AllowFPExt, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) {
----------------
wangpc-pp wrote:

Since we have ExtKind now, can we use mask (an integer) to represent `AllowSExt`, `AllowZExt` and `AllowFPExt`.
Sample code:
```
enum class ExtKind { ZExt = 1 << 0, SExt = 1 << 1, FPExt = 1 << 2 };

canFoldToVWWithSameExtensionImpl(..., ZExt | SExt ,...)

if (Mask & ZExt && LHS.SupportsZExt && RHS.SupportsZExt)
  //...
```

https://github.com/llvm/llvm-project/pull/81248