[llvm] e7291ff - [RISCV] Recognize CSR name ssp for Zicfilp. (#81974)

[via llvm-commits]

Author: Yeting Kuo
Date: 2024-02-17T09:56:22+08:00
New Revision: e7291ff02d7e262ab9452bc7eb058b6d3dc65a40

URL: https://github.com/llvm/llvm-project/commit/e7291ff02d7e262ab9452bc7eb058b6d3dc65a40
DIFF: https://github.com/llvm/llvm-project/commit/e7291ff02d7e262ab9452bc7eb058b6d3dc65a40.diff

LOG: [RISCV] Recognize CSR name ssp for Zicfilp. (#81974)

The CSR address of `ssp` is 0x011.
Ref:
https://github.com/riscv/riscv-cfi/blob/main/cfi_backward.adoc#shadow-stack-pointer-ssp

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSystemOperands.td
    llvm/test/MC/RISCV/user-csr-names.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index f046312b1d4284..79f977e5b32266 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -342,6 +342,11 @@ def SysRegVL : SysReg<"vl", 0xC20>;
 def : SysReg<"vtype", 0xC21>;
 def SysRegVLENB: SysReg<"vlenb", 0xC22>;
 
+//===----------------------------------------------------------------------===//
+// Shadow Stack CSR
+//===----------------------------------------------------------------------===//
+def : SysReg<"ssp", 0x011>;
+
 //===----------------------------------------------------------------------===//
 // State Enable Extension (Smstateen)
 //===----------------------------------------------------------------------===//

diff  --git a/llvm/test/MC/RISCV/user-csr-names.s b/llvm/test/MC/RISCV/user-csr-names.s
index 9f8f029e564275..f49eace659ac91 100644
--- a/llvm/test/MC/RISCV/user-csr-names.s
+++ b/llvm/test/MC/RISCV/user-csr-names.s
@@ -61,6 +61,20 @@ csrrs t1, instret, zero
 # uimm12
 csrrs t2, 0xC02, zero
 
+# ssp
+# name
+# CHECK-INST: csrrs t1, ssp, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x10,0x01]
+# CHECK-INST-ALIAS: csrr t1, ssp
+# uimm12
+# CHECK-INST: csrrs t2, ssp, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x10,0x01]
+# CHECK-INST-ALIAS: csrr t2, ssp
+# name
+csrrs t1, ssp, zero
+# uimm12
+csrrs t2, 0x011, zero
+
 # hpmcounter3
 # name
 # CHECK-INST: csrrs t1, hpmcounter3, zero