[llvm] [NFC] Precommit a coroutine test for LoopRotate (PR #82031)
Alan Zhao via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 16 11:33:27 PST 2024
https://github.com/alanzhao1 updated https://github.com/llvm/llvm-project/pull/82031
>From 28a48a486f0f426594e2d477f98701837354568d Mon Sep 17 00:00:00 2001
From: Alan Zhao <ayzhao at google.com>
Date: Fri, 16 Feb 2024 11:28:03 -0800
Subject: [PATCH 1/2] [NFC] Precommit a coroutine test for LoopRotate
This is to provide a baseline test for
https://github.com/llvm/llvm-project/pull/81937.
---
.../Analysis/CostModel/RISCV/rvv-shuffle.ll | 4 +-
.../CostModel/RISCV/rvv-vectorextract.ll | 56 +-
.../RISCV/shuffle-extract_subvector.ll | 72 +-
llvm/test/CodeGen/AArch64/arm64-stur.ll | 5 +-
llvm/test/CodeGen/AArch64/merge-store.ll | 3 +-
.../AArch64/storepairsuppress_minsize.ll | 92 +-
.../RISCV/atomic-cmpxchg-branch-on-result.ll | 22 -
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll | 1122 +-
llvm/test/CodeGen/RISCV/atomic-rmw.ll | 14410 +++++-----------
llvm/test/Transforms/InstCombine/fsh.ll | 128 -
.../InstCombine/struct-assign-tbaa.ll | 5 +-
llvm/test/Transforms/LoopRotate/coroutine.ll | 47 +
.../LoopVectorize/trunc-reductions.ll | 65 -
.../SLPVectorizer/AArch64/horizontal.ll | 46 +-
.../Transforms/SLPVectorizer/X86/PR35777.ll | 22 +-
.../SLPVectorizer/X86/minimum-sizes.ll | 88 +-
.../X86/multi-node-with-save-values.ll | 6 +-
.../SLPVectorizer/X86/vectorize-cmps.ll | 12 +-
llvm/test/Transforms/SROA/tbaa-struct2.ll | 21 +-
llvm/test/Transforms/SROA/tbaa-struct3.ll | 80 +-
.../ELF/binary-output-target.test | 6 -
.../llvm-objcopy/ELF/cross-arch-headers.test | 7 -
22 files changed, 4396 insertions(+), 11923 deletions(-)
create mode 100644 llvm/test/Transforms/LoopRotate/coroutine.ll
diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
index 30da63b3feec65..4f3c7e2f90c655 100644
--- a/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
@@ -52,14 +52,14 @@ define void @vector_broadcast() {
define void @vector_insert_extract(<vscale x 4 x i32> %v0, <vscale x 16 x i32> %v1, <16 x i32> %v2) {
; CHECK-LABEL: 'vector_insert_extract'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %insert_fixed_into_scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> %v0, <16 x i32> %v2, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %extract_scalable_from_scalable = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %v1, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %insert_scalable_into_scalable = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> %v1, <vscale x 4 x i32> %v0, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'vector_insert_extract'
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %insert_fixed_into_scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> %v0, <16 x i32> %v2, i64 0)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %extract_scalable_from_scalable = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %v1, i64 0)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %insert_scalable_into_scalable = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> %v1, <vscale x 4 x i32> %v0, i64 0)
diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-vectorextract.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-vectorextract.ll
index 61f80b643cf78d..1e2d1f4d94954e 100644
--- a/llvm/test/Analysis/CostModel/RISCV/rvv-vectorextract.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/rvv-vectorextract.ll
@@ -11,13 +11,13 @@ define void @vector_extract_nxv128i8_0(<vscale x 128 x i8> %v) {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %scalable_m2 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %scalable_m4 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %scalable_m8 = call <vscale x 64 x i8> @llvm.vector.extract.nxv64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'vector_extract_nxv128i8_0'
@@ -28,13 +28,13 @@ define void @vector_extract_nxv128i8_0(<vscale x 128 x i8> %v) {
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %scalable_m2 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %scalable_m4 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %scalable_m8 = call <vscale x 64 x i8> @llvm.vector.extract.nxv64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%scalable_mf8 = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
@@ -110,23 +110,23 @@ define void @vector_extract_nxv128i8_1(<vscale x 128 x i8> %v) {
define void @vector_extract_v128i8_0(<128 x i8> %v) {
; CHECK-LABEL: 'vector_extract_v128i8_0'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.v128i8(<128 x i8> %v, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'vector_extract_v128i8_0'
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.v128i8(<128 x i8> %v, i64 0)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
diff --git a/llvm/test/Analysis/CostModel/RISCV/shuffle-extract_subvector.ll b/llvm/test/Analysis/CostModel/RISCV/shuffle-extract_subvector.ll
index 793786318a0a16..76cb1955a2b377 100644
--- a/llvm/test/Analysis/CostModel/RISCV/shuffle-extract_subvector.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/shuffle-extract_subvector.ll
@@ -9,13 +9,13 @@
define void @test_vXf64(<4 x double> %src256, <8 x double> %src512) {
; CHECK-LABEL: 'test_vXf64'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_01 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_01 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_23 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32> <i32 2, i32 3>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_01 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_01 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_23 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_45 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_67 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32> <i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_0123 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_0123 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_2345 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_4567 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of -1 for instruction: %V512_567u = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32> <i32 5, i32 6, i32 7, i32 poison>
@@ -36,13 +36,13 @@ define void @test_vXf64(<4 x double> %src256, <8 x double> %src512) {
define void @test_vXi64(<4 x i64> %src256, <8 x i64> %src512) {
; CHECK-LABEL: 'test_vXi64'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_01 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_01 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_23 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32> <i32 2, i32 3>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_01 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_01 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_23 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_45 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_67 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32> <i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_0123 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_0123 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_2345 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_4567 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
@@ -61,15 +61,15 @@ define void @test_vXi64(<4 x i64> %src256, <8 x i64> %src512) {
define void @test_vXi32(<4 x i32> %src128, <8 x i32> %src256, <16 x i32> %src512) {
; CHECK-LABEL: 'test_vXi32'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V128_01 = shufflevector <4 x i32> %src128, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_01 = shufflevector <4 x i32> %src128, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_23 = shufflevector <4 x i32> %src128, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_01 = shufflevector <8 x i32> %src256, <8 x i32> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_01 = shufflevector <8 x i32> %src256, <8 x i32> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_23 = shufflevector <8 x i32> %src256, <8 x i32> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_45 = shufflevector <8 x i32> %src256, <8 x i32> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_67 = shufflevector <8 x i32> %src256, <8 x i32> undef, <2 x i32> <i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_0123 = shufflevector <8 x i32> %src256, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_0123 = shufflevector <8 x i32> %src256, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_4567 = shufflevector <8 x i32> %src256, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_01 = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_01 = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_23 = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_45 = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_67 = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 6, i32 7>
@@ -77,11 +77,11 @@ define void @test_vXi32(<4 x i32> %src128, <8 x i32> %src256, <16 x i32> %src512
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_AB = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 10, i32 11>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_CD = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 12, i32 13>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_EF = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_0123 = shufflevector <16 x i32> %src512, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_0123 = shufflevector <16 x i32> %src512, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_4567 = shufflevector <16 x i32> %src512, <16 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_89AB = shufflevector <16 x i32> %src512, <16 x i32> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_CDEF = shufflevector <16 x i32> %src512, <16 x i32> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_01234567 = shufflevector <16 x i32> %src512, <16 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_01234567 = shufflevector <16 x i32> %src512, <16 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_89ABCDEF = shufflevector <16 x i32> %src512, <16 x i32> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
@@ -112,15 +112,15 @@ define void @test_vXi32(<4 x i32> %src128, <8 x i32> %src256, <16 x i32> %src512
define void @test_vXi16(<4 x i16> %src64, <8 x i16> %src128, <16 x i16> %src256, <32 x i16> %src512) {
; CHECK-LABEL: 'test_vXi16'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V64_01 = shufflevector <4 x i16> %src64, <4 x i16> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_01 = shufflevector <4 x i16> %src64, <4 x i16> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_23 = shufflevector <4 x i16> %src64, <4 x i16> undef, <2 x i32> <i32 2, i32 3>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V128_01 = shufflevector <8 x i16> %src128, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_01 = shufflevector <8 x i16> %src128, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_23 = shufflevector <8 x i16> %src128, <8 x i16> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_45 = shufflevector <8 x i16> %src128, <8 x i16> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_67 = shufflevector <8 x i16> %src128, <8 x i16> undef, <2 x i32> <i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V128_0123 = shufflevector <8 x i16> %src128, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_0123 = shufflevector <8 x i16> %src128, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_4567 = shufflevector <8 x i16> %src128, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_01 = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_01 = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_23 = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_45 = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_67 = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 6, i32 7>
@@ -128,15 +128,15 @@ define void @test_vXi16(<4 x i16> %src64, <8 x i16> %src128, <16 x i16> %src256,
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_AB = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 10, i32 11>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_CD = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 12, i32 13>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_EF = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_0123 = shufflevector <16 x i16> %src256, <16 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_0123 = shufflevector <16 x i16> %src256, <16 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_2345 = shufflevector <16 x i16> %src256, <16 x i16> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_4567 = shufflevector <16 x i16> %src256, <16 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_6789 = shufflevector <16 x i16> %src256, <16 x i16> undef, <4 x i32> <i32 6, i32 7, i32 8, i32 9>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_89AB = shufflevector <16 x i16> %src256, <16 x i16> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_CDEF = shufflevector <16 x i16> %src256, <16 x i16> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_01234567 = shufflevector <16 x i16> %src256, <16 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_01234567 = shufflevector <16 x i16> %src256, <16 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_89ABCDEF = shufflevector <16 x i16> %src256, <16 x i16> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01 = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01 = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_02_03 = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_04_05 = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_06_07 = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 6, i32 7>
@@ -152,7 +152,7 @@ define void @test_vXi16(<4 x i16> %src64, <8 x i16> %src128, <16 x i16> %src256,
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_1A_1B = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 26, i32 27>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_1C_1D = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 28, i32 29>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_1E_1F = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 30, i32 31>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01_02_03 = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01_02_03 = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_02_03_04_05 = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_04_05_06_07 = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_06_07_08_09 = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 6, i32 7, i32 8, i32 9>
@@ -162,11 +162,11 @@ define void @test_vXi16(<4 x i16> %src64, <8 x i16> %src128, <16 x i16> %src256,
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_14_15_16_17 = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 20, i32 21, i32 22, i32 23>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_18_19_1A_1B = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 24, i32 25, i32 26, i32 27>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_1C_1D_1E_1F = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 28, i32 29, i32 30, i32 31>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01_02_03_04_05_06_07 = shufflevector <32 x i16> %src512, <32 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01_02_03_04_05_06_07 = shufflevector <32 x i16> %src512, <32 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_08_09_0A_0B_0C_0D_0E_0F = shufflevector <32 x i16> %src512, <32 x i16> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_10_11_12_13_14_15_16_17 = shufflevector <32 x i16> %src512, <32 x i16> undef, <8 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_18_19_1A_1B_1C_1D_1E_1F = shufflevector <32 x i16> %src512, <32 x i16> undef, <8 x i32> <i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F = shufflevector <32 x i16> %src512, <32 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F = shufflevector <32 x i16> %src512, <32 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_10_11_12_13_14_15_16_17_18_19_1A_1B_1C_1D_1E_1F = shufflevector <32 x i16> %src512, <32 x i16> undef, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
@@ -231,13 +231,13 @@ define void @test_vXi16(<4 x i16> %src64, <8 x i16> %src128, <16 x i16> %src256,
define void @test_vXi8(<8 x i8> %src64, <16 x i8> %src128, <32 x i8> %src256, <64 x i8> %src512) {
; CHECK-LABEL: 'test_vXi8'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V64_01 = shufflevector <8 x i8> %src64, <8 x i8> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_01 = shufflevector <8 x i8> %src64, <8 x i8> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_23 = shufflevector <8 x i8> %src64, <8 x i8> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_45 = shufflevector <8 x i8> %src64, <8 x i8> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_67 = shufflevector <8 x i8> %src64, <8 x i8> undef, <2 x i32> <i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V64_0123 = shufflevector <8 x i8> %src64, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_0123 = shufflevector <8 x i8> %src64, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_4567 = shufflevector <8 x i8> %src64, <8 x i8> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V128_01 = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_01 = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_23 = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_45 = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_67 = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 6, i32 7>
@@ -245,15 +245,15 @@ define void @test_vXi8(<8 x i8> %src64, <16 x i8> %src128, <32 x i8> %src256, <6
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_AB = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 10, i32 11>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_CD = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 12, i32 13>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_EF = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V128_0123 = shufflevector <16 x i8> %src128, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_0123 = shufflevector <16 x i8> %src128, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_2345 = shufflevector <16 x i8> %src128, <16 x i8> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_4567 = shufflevector <16 x i8> %src128, <16 x i8> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_6789 = shufflevector <16 x i8> %src128, <16 x i8> undef, <4 x i32> <i32 6, i32 7, i32 8, i32 9>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_89AB = shufflevector <16 x i8> %src128, <16 x i8> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_CDEF = shufflevector <16 x i8> %src128, <16 x i8> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V128_01234567 = shufflevector <16 x i8> %src128, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_01234567 = shufflevector <16 x i8> %src128, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_89ABCDEF = shufflevector <16 x i8> %src128, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_00_01 = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_00_01 = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_02_03 = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_04_05 = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_06_07 = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 6, i32 7>
@@ -269,7 +269,7 @@ define void @test_vXi8(<8 x i8> %src64, <16 x i8> %src128, <32 x i8> %src256, <6
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_1A_1B = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 26, i32 27>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_1C_1D = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 28, i32 29>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_1E_1F = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 30, i32 31>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_00_01_02_03 = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_00_01_02_03 = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_02_03_04_05 = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_04_05_06_07 = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_06_07_08_09 = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 6, i32 7, i32 8, i32 9>
@@ -279,13 +279,13 @@ define void @test_vXi8(<8 x i8> %src64, <16 x i8> %src128, <32 x i8> %src256, <6
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_14_15_16_17 = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 20, i32 21, i32 22, i32 23>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_18_19_1A_1B = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 24, i32 25, i32 26, i32 27>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_1C_1D_1E_1F = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 28, i32 29, i32 30, i32 31>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_00_01_02_03_04_05_06_07 = shufflevector <32 x i8> %src256, <32 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_00_01_02_03_04_05_06_07 = shufflevector <32 x i8> %src256, <32 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_08_09_0A_0B_0C_0D_0E_0F = shufflevector <32 x i8> %src256, <32 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_10_11_12_13_14_15_16_17 = shufflevector <32 x i8> %src256, <32 x i8> undef, <8 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_18_19_1A_1B_1C_1D_1E_1F = shufflevector <32 x i8> %src256, <32 x i8> undef, <8 x i32> <i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F = shufflevector <32 x i8> %src256, <32 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F = shufflevector <32 x i8> %src256, <32 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_10_11_12_13_14_15_16_17_18_19_1A_1B_1C_1D_1E_1F = shufflevector <32 x i8> %src256, <32 x i8> undef, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01 = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01 = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_02_03 = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_04_05 = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_06_07 = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 6, i32 7>
@@ -317,7 +317,7 @@ define void @test_vXi8(<8 x i8> %src64, <16 x i8> %src128, <32 x i8> %src256, <6
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_3A_3B = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 58, i32 59>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_3C_3D = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 60, i32 61>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_3E_3F = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 62, i32 63>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01_02_03 = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01_02_03 = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_04_05_06_07 = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_08_09_0A_0B = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_0C_0D_0E_0F = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
@@ -333,7 +333,7 @@ define void @test_vXi8(<8 x i8> %src64, <16 x i8> %src128, <32 x i8> %src256, <6
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_34_35_36_37 = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 52, i32 53, i32 54, i32 55>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_38_39_3A_3B = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 56, i32 57, i32 58, i32 59>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_3C_3D_3E_3F = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 60, i32 61, i32 62, i32 63>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01_02_03_04_05_06_07 = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01_02_03_04_05_06_07 = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_08_09_0A_0B_0C_0D_0E_0F = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_10_11_12_13_14_15_16_17 = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_18_19_1A_1B_1C_1D_1E_1F = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
@@ -341,11 +341,11 @@ define void @test_vXi8(<8 x i8> %src64, <16 x i8> %src128, <32 x i8> %src256, <6
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_28_29_2A_2B_2C_2D_2E_2F = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_30_31_32_33_34_35_36_37 = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_38_39_3A_3B_3C_3D_3E_3F = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F = shufflevector <64 x i8> %src512, <64 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F = shufflevector <64 x i8> %src512, <64 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_10_11_12_13_14_15_16_17_18_19_1A_1B_1C_1D_1E_1F = shufflevector <64 x i8> %src512, <64 x i8> undef, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_20_21_22_23_24_25_26_27_28_29_2A_2B_2C_2D_2E_2F = shufflevector <64 x i8> %src512, <64 x i8> undef, <16 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_30_31_32_33_34_35_36_37_38_39_3A_3B_3C_3D_3E_3F = shufflevector <64 x i8> %src512, <64 x i8> undef, <16 x i32> <i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F_10_11_12_13_14_15_16_17_18_19_1A_1B_1C_1D_1E_1F = shufflevector <64 x i8> %src512, <64 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F_10_11_12_13_14_15_16_17_18_19_1A_1B_1C_1D_1E_1F = shufflevector <64 x i8> %src512, <64 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_20_21_22_23_24_25_26_27_28_29_2A_2B_2C_2D_2E_2F_30_31_32_33_34_35_36_37_38_39_3A_3B_3C_3D_3E_3F = shufflevector <64 x i8> %src512, <64 x i8> undef, <32 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
diff --git a/llvm/test/CodeGen/AArch64/arm64-stur.ll b/llvm/test/CodeGen/AArch64/arm64-stur.ll
index 7d9de9e28ff5c0..2a74abb10226da 100644
--- a/llvm/test/CodeGen/AArch64/arm64-stur.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-stur.ll
@@ -65,8 +65,9 @@ declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind
; CHECK-LABEL: unaligned:
; CHECK-NOT: str q0
-; CHECK: ext.16b v[[REG2:[0-9]+]], v[[REG:[0-9]+]], v[[REG]], #8
-; CHECK: stp d[[REG]], d[[REG2]], [x0]
+; CHECK: str d[[REG:[0-9]+]], [x0]
+; CHECK: ext.16b v[[REG2:[0-9]+]], v[[REG]], v[[REG]], #8
+; CHECK: str d[[REG2]], [x0, #8]
define void @unaligned(ptr %p, <4 x i32> %v) nounwind {
store <4 x i32> %v, ptr %p, align 4
ret void
diff --git a/llvm/test/CodeGen/AArch64/merge-store.ll b/llvm/test/CodeGen/AArch64/merge-store.ll
index 6653984562ae6d..b93d0c3bc96086 100644
--- a/llvm/test/CodeGen/AArch64/merge-store.ll
+++ b/llvm/test/CodeGen/AArch64/merge-store.ll
@@ -45,7 +45,8 @@ define void @merge_vec_extract_stores(<4 x float> %v1, ptr %ptr) {
; SPLITTING-LABEL: merge_vec_extract_stores:
; SPLITTING: // %bb.0:
; SPLITTING-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; SPLITTING-NEXT: stp d0, d1, [x0, #24]
+; SPLITTING-NEXT: str d0, [x0, #24]
+; SPLITTING-NEXT: str d1, [x0, #32]
; SPLITTING-NEXT: ret
;
; MISALIGNED-LABEL: merge_vec_extract_stores:
diff --git a/llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll b/llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll
index 93fb9c1bc4b9d0..6d1986ebb8182b 100644
--- a/llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll
+++ b/llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll
@@ -1,56 +1,72 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64 -mcpu=apple-m1 -mattr=+store-pair-suppress -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mcpu=cortex-a55 -mattr=+store-pair-suppress -o - %s | FileCheck %s
; Check that stp are not suppressed at minsize.
-define void @test_default(ptr %dst, <8 x i32> %v0) {
+%T_IN_BLOCK = type [ 2 x { double, { double, double } } ]
+declare %T_IN_BLOCK @return_in_block()
+ at in_block_store = dso_local global %T_IN_BLOCK zeroinitializer, align 8
+
+define void @test_default() uwtable {
; CHECK-LABEL: test_default:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: xtn v0.8b, v0.8h
-; CHECK-NEXT: mul v1.8b, v0.8b, v0.8b
-; CHECK-NEXT: str d1, [x0, #8]
-; CHECK-NEXT: str d0, [x0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl return_in_block
+; CHECK-NEXT: adrp x8, in_block_store
+; CHECK-NEXT: add x8, x8, :lo12:in_block_store
+; CHECK-NEXT: str d0, [x8]
+; CHECK-NEXT: str d1, [x8, #8]
+; CHECK-NEXT: str d2, [x8, #16]
+; CHECK-NEXT: str d3, [x8, #24]
+; CHECK-NEXT: str d4, [x8, #32]
+; CHECK-NEXT: str d5, [x8, #40]
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: ret
-entry:
- %add.ptr.1 = getelementptr i8, ptr %dst, i64 8
- %t = trunc <8 x i32> %v0 to <8 x i8>
- %mul = mul <8 x i8> %t, %t
- store <8 x i8> %mul, ptr %add.ptr.1, align 1
- store <8 x i8> %t, ptr %dst, align 1
+ %1 = call %T_IN_BLOCK @return_in_block()
+ store %T_IN_BLOCK %1, ptr @in_block_store
ret void
}
-define void @test_minsize(ptr %dst, <8 x i32> %v0) minsize {
+define void @test_minsize() minsize uwtable {
; CHECK-LABEL: test_minsize:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: xtn v0.8b, v0.8h
-; CHECK-NEXT: mul v1.8b, v0.8b, v0.8b
-; CHECK-NEXT: stp d0, d1, [x0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl return_in_block
+; CHECK-NEXT: adrp x8, in_block_store
+; CHECK-NEXT: add x8, x8, :lo12:in_block_store
+; CHECK-NEXT: stp d0, d1, [x8]
+; CHECK-NEXT: stp d2, d3, [x8, #16]
+; CHECK-NEXT: stp d4, d5, [x8, #32]
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
-entry:
- %add.ptr.1 = getelementptr i8, ptr %dst, i64 8
- %t = trunc <8 x i32> %v0 to <8 x i8>
- %mul = mul <8 x i8> %t, %t
- store <8 x i8> %mul, ptr %add.ptr.1, align 1
- store <8 x i8> %t, ptr %dst, align 1
+ %1 = call %T_IN_BLOCK @return_in_block()
+ store %T_IN_BLOCK %1, ptr @in_block_store
ret void
}
-define void @test_optsize(ptr %dst, <8 x i32> %v0) optsize {
+define void @test_optsize() optsize uwtable {
; CHECK-LABEL: test_optsize:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: xtn v0.8b, v0.8h
-; CHECK-NEXT: mul v1.8b, v0.8b, v0.8b
-; CHECK-NEXT: stp d0, d1, [x0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl return_in_block
+; CHECK-NEXT: adrp x8, in_block_store
+; CHECK-NEXT: add x8, x8, :lo12:in_block_store
+; CHECK-NEXT: stp d0, d1, [x8]
+; CHECK-NEXT: stp d2, d3, [x8, #16]
+; CHECK-NEXT: stp d4, d5, [x8, #32]
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: ret
-entry:
- %add.ptr.1 = getelementptr i8, ptr %dst, i64 8
- %t = trunc <8 x i32> %v0 to <8 x i8>
- %mul = mul <8 x i8> %t, %t
- store <8 x i8> %mul, ptr %add.ptr.1, align 1
- store <8 x i8> %t, ptr %dst, align 1
+ %1 = call %T_IN_BLOCK @return_in_block()
+ store %T_IN_BLOCK %1, ptr @in_block_store
ret void
}
diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
index 90d78779b764d2..a8477cc550fe6a 100644
--- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
@@ -7,8 +7,6 @@
; RUN: | FileCheck -check-prefixes=NOZACAS,RV64IA %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=ZACAS,RV64IA-ZACAS %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas,+experimental-zabha -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=ZACAS,RV64IA-ZABHA %s
; Test cmpxchg followed by a branch on the cmpxchg success value to see if the
; branch is folded into the cmpxchg expansion.
@@ -211,16 +209,6 @@ define void @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %v
; RV64IA-ZACAS-NEXT: # %bb.5: # %do_cmpxchg
; RV64IA-ZACAS-NEXT: # %bb.2: # %exit
; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-ZABHA-LABEL: cmpxchg_masked_and_branch1:
-; RV64IA-ZABHA: # %bb.0: # %entry
-; RV64IA-ZABHA-NEXT: .LBB2_1: # %do_cmpxchg
-; RV64IA-ZABHA-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZABHA-NEXT: mv a3, a1
-; RV64IA-ZABHA-NEXT: amocas.b.aqrl a3, a2, (a0)
-; RV64IA-ZABHA-NEXT: bne a3, a1, .LBB2_1
-; RV64IA-ZABHA-NEXT: # %bb.2: # %exit
-; RV64IA-ZABHA-NEXT: ret
entry:
br label %do_cmpxchg
do_cmpxchg:
@@ -363,16 +351,6 @@ define void @cmpxchg_masked_and_branch2(ptr %ptr, i8 signext %cmp, i8 signext %v
; RV64IA-ZACAS-NEXT: beq a1, a4, .LBB3_1
; RV64IA-ZACAS-NEXT: # %bb.2: # %exit
; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-ZABHA-LABEL: cmpxchg_masked_and_branch2:
-; RV64IA-ZABHA: # %bb.0: # %entry
-; RV64IA-ZABHA-NEXT: .LBB3_1: # %do_cmpxchg
-; RV64IA-ZABHA-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZABHA-NEXT: mv a3, a1
-; RV64IA-ZABHA-NEXT: amocas.b.aqrl a3, a2, (a0)
-; RV64IA-ZABHA-NEXT: beq a3, a1, .LBB3_1
-; RV64IA-ZABHA-NEXT: # %bb.2: # %exit
-; RV64IA-ZABHA-NEXT: ret
entry:
br label %do_cmpxchg
do_cmpxchg:
diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
index 8df37bf40975c1..5b3e5789e8d910 100644
--- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
@@ -15,14 +15,10 @@
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-WMO-ZACAS %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas,+experimental-zabha -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZABHA,RV64IA-WMO-ZABHA %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+experimental-zacas -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-TSO-ZACAS %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+experimental-zacas,+experimental-zabha -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZABHA,RV64IA-TSO-ZABHA %s
define void @cmpxchg_i8_monotonic_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_monotonic_monotonic:
@@ -74,79 +70,28 @@ define void @cmpxchg_i8_monotonic_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: cmpxchg_i8_monotonic_monotonic:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a3, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a4, 255
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: andi a2, a2, 255
-; RV64IA-WMO-NEXT: sllw a0, a2, a0
-; RV64IA-WMO-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a2, (a3)
-; RV64IA-WMO-NEXT: and a5, a2, a4
-; RV64IA-WMO-NEXT: bne a5, a1, .LBB0_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a2, a0
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a2, a5
-; RV64IA-WMO-NEXT: sc.w a5, a5, (a3)
-; RV64IA-WMO-NEXT: bnez a5, .LBB0_1
-; RV64IA-WMO-NEXT: .LBB0_3:
-; RV64IA-WMO-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: cmpxchg_i8_monotonic_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a3, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a4, 255
-; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: andi a2, a2, 255
-; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
-; RV64IA-ZACAS-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a2, (a3)
-; RV64IA-ZACAS-NEXT: and a5, a2, a4
-; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB0_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a5, a2, a0
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a2, a5
-; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a3)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB0_1
-; RV64IA-ZACAS-NEXT: .LBB0_3:
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-ZABHA-LABEL: cmpxchg_i8_monotonic_monotonic:
-; RV64IA-ZABHA: # %bb.0:
-; RV64IA-ZABHA-NEXT: amocas.b a1, a2, (a0)
-; RV64IA-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-LABEL: cmpxchg_i8_monotonic_monotonic:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a3, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a4, 255
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: andi a2, a2, 255
-; RV64IA-TSO-NEXT: sllw a0, a2, a0
-; RV64IA-TSO-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a2, (a3)
-; RV64IA-TSO-NEXT: and a5, a2, a4
-; RV64IA-TSO-NEXT: bne a5, a1, .LBB0_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a2, a0
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a2, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a3)
-; RV64IA-TSO-NEXT: bnez a5, .LBB0_1
-; RV64IA-TSO-NEXT: .LBB0_3:
-; RV64IA-TSO-NEXT: ret
+; RV64IA-LABEL: cmpxchg_i8_monotonic_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a4, 255
+; RV64IA-NEXT: sllw a4, a4, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: sllw a0, a2, a0
+; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a2, (a3)
+; RV64IA-NEXT: and a5, a2, a4
+; RV64IA-NEXT: bne a5, a1, .LBB0_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
+; RV64IA-NEXT: xor a5, a2, a0
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a2, a5
+; RV64IA-NEXT: sc.w a5, a5, (a3)
+; RV64IA-NEXT: bnez a5, .LBB0_1
+; RV64IA-NEXT: .LBB0_3:
+; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val monotonic monotonic
ret void
}
@@ -316,11 +261,6 @@ define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-ZACAS-NEXT: .LBB1_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_acquire_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.b.aq a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i8_acquire_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -366,11 +306,6 @@ define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB1_1
; RV64IA-TSO-ZACAS-NEXT: .LBB1_3:
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_acquire_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire monotonic
ret void
}
@@ -540,11 +475,6 @@ define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-ZACAS-NEXT: .LBB2_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_acquire_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.b.aq a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i8_acquire_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -590,11 +520,6 @@ define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB2_1
; RV64IA-TSO-ZACAS-NEXT: .LBB2_3:
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_acquire_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire acquire
ret void
}
@@ -764,11 +689,6 @@ define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-ZACAS-NEXT: .LBB3_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_release_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.b.rl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i8_release_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -814,11 +734,6 @@ define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB3_1
; RV64IA-TSO-ZACAS-NEXT: .LBB3_3:
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_release_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release monotonic
ret void
}
@@ -988,11 +903,6 @@ define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-ZACAS-NEXT: .LBB4_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_release_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.b.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i8_release_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -1038,11 +948,6 @@ define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB4_1
; RV64IA-TSO-ZACAS-NEXT: .LBB4_3:
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_release_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release acquire
ret void
}
@@ -1212,11 +1117,6 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-ZACAS-NEXT: .LBB5_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_acq_rel_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.b.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -1262,11 +1162,6 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB5_1
; RV64IA-TSO-ZACAS-NEXT: .LBB5_3:
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_acq_rel_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel monotonic
ret void
}
@@ -1436,11 +1331,6 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-ZACAS-NEXT: .LBB6_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_acq_rel_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.b.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -1486,11 +1376,6 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB6_1
; RV64IA-TSO-ZACAS-NEXT: .LBB6_3:
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_acq_rel_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel acquire
ret void
}
@@ -1545,84 +1430,28 @@ define void @cmpxchg_i8_seq_cst_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: cmpxchg_i8_seq_cst_monotonic:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a3, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a4, 255
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: andi a2, a2, 255
-; RV64IA-WMO-NEXT: sllw a0, a2, a0
-; RV64IA-WMO-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-WMO-NEXT: and a5, a2, a4
-; RV64IA-WMO-NEXT: bne a5, a1, .LBB7_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a2, a0
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a2, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a3)
-; RV64IA-WMO-NEXT: bnez a5, .LBB7_1
-; RV64IA-WMO-NEXT: .LBB7_3:
-; RV64IA-WMO-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: cmpxchg_i8_seq_cst_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a3, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a4, 255
-; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: andi a2, a2, 255
-; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
-; RV64IA-ZACAS-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-ZACAS-NEXT: and a5, a2, a4
-; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB7_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a5, a2, a0
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a2, a5
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB7_1
-; RV64IA-ZACAS-NEXT: .LBB7_3:
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_seq_cst_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.b.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-LABEL: cmpxchg_i8_seq_cst_monotonic:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a3, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a4, 255
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: andi a2, a2, 255
-; RV64IA-TSO-NEXT: sllw a0, a2, a0
-; RV64IA-TSO-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-TSO-NEXT: and a5, a2, a4
-; RV64IA-TSO-NEXT: bne a5, a1, .LBB7_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a2, a0
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a2, a5
-; RV64IA-TSO-NEXT: sc.w.rl a5, a5, (a3)
-; RV64IA-TSO-NEXT: bnez a5, .LBB7_1
-; RV64IA-TSO-NEXT: .LBB7_3:
-; RV64IA-TSO-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_seq_cst_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: cmpxchg_i8_seq_cst_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a4, 255
+; RV64IA-NEXT: sllw a4, a4, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: sllw a0, a2, a0
+; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-NEXT: and a5, a2, a4
+; RV64IA-NEXT: bne a5, a1, .LBB7_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
+; RV64IA-NEXT: xor a5, a2, a0
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a2, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-NEXT: bnez a5, .LBB7_1
+; RV64IA-NEXT: .LBB7_3:
+; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst monotonic
ret void
}
@@ -1677,84 +1506,28 @@ define void @cmpxchg_i8_seq_cst_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: cmpxchg_i8_seq_cst_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a3, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a4, 255
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: andi a2, a2, 255
-; RV64IA-WMO-NEXT: sllw a0, a2, a0
-; RV64IA-WMO-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-WMO-NEXT: and a5, a2, a4
-; RV64IA-WMO-NEXT: bne a5, a1, .LBB8_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a2, a0
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a2, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a3)
-; RV64IA-WMO-NEXT: bnez a5, .LBB8_1
-; RV64IA-WMO-NEXT: .LBB8_3:
-; RV64IA-WMO-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: cmpxchg_i8_seq_cst_acquire:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a3, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a4, 255
-; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: andi a2, a2, 255
-; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
-; RV64IA-ZACAS-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-ZACAS-NEXT: and a5, a2, a4
-; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB8_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a5, a2, a0
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a2, a5
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB8_1
-; RV64IA-ZACAS-NEXT: .LBB8_3:
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_seq_cst_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.b.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-LABEL: cmpxchg_i8_seq_cst_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a3, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a4, 255
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: andi a2, a2, 255
-; RV64IA-TSO-NEXT: sllw a0, a2, a0
-; RV64IA-TSO-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-TSO-NEXT: and a5, a2, a4
-; RV64IA-TSO-NEXT: bne a5, a1, .LBB8_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a2, a0
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a2, a5
-; RV64IA-TSO-NEXT: sc.w.rl a5, a5, (a3)
-; RV64IA-TSO-NEXT: bnez a5, .LBB8_1
-; RV64IA-TSO-NEXT: .LBB8_3:
-; RV64IA-TSO-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_seq_cst_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: cmpxchg_i8_seq_cst_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a4, 255
+; RV64IA-NEXT: sllw a4, a4, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: sllw a0, a2, a0
+; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-NEXT: and a5, a2, a4
+; RV64IA-NEXT: bne a5, a1, .LBB8_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
+; RV64IA-NEXT: xor a5, a2, a0
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a2, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-NEXT: bnez a5, .LBB8_1
+; RV64IA-NEXT: .LBB8_3:
+; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst acquire
ret void
}
@@ -1809,84 +1582,28 @@ define void @cmpxchg_i8_seq_cst_seq_cst(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: cmpxchg_i8_seq_cst_seq_cst:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a3, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a4, 255
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: andi a2, a2, 255
-; RV64IA-WMO-NEXT: sllw a0, a2, a0
-; RV64IA-WMO-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-WMO-NEXT: and a5, a2, a4
-; RV64IA-WMO-NEXT: bne a5, a1, .LBB9_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a2, a0
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a2, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a3)
-; RV64IA-WMO-NEXT: bnez a5, .LBB9_1
-; RV64IA-WMO-NEXT: .LBB9_3:
-; RV64IA-WMO-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: cmpxchg_i8_seq_cst_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a3, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a4, 255
-; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: andi a2, a2, 255
-; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
-; RV64IA-ZACAS-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-ZACAS-NEXT: and a5, a2, a4
-; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB9_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a5, a2, a0
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a2, a5
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB9_1
-; RV64IA-ZACAS-NEXT: .LBB9_3:
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.b.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-LABEL: cmpxchg_i8_seq_cst_seq_cst:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a3, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a4, 255
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: andi a2, a2, 255
-; RV64IA-TSO-NEXT: sllw a0, a2, a0
-; RV64IA-TSO-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-TSO-NEXT: and a5, a2, a4
-; RV64IA-TSO-NEXT: bne a5, a1, .LBB9_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a2, a0
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a2, a5
-; RV64IA-TSO-NEXT: sc.w.rl a5, a5, (a3)
-; RV64IA-TSO-NEXT: bnez a5, .LBB9_1
-; RV64IA-TSO-NEXT: .LBB9_3:
-; RV64IA-TSO-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a4, 255
+; RV64IA-NEXT: sllw a4, a4, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: andi a2, a2, 255
+; RV64IA-NEXT: sllw a0, a2, a0
+; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-NEXT: and a5, a2, a4
+; RV64IA-NEXT: bne a5, a1, .LBB9_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
+; RV64IA-NEXT: xor a5, a2, a0
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a2, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-NEXT: bnez a5, .LBB9_1
+; RV64IA-NEXT: .LBB9_3:
+; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst seq_cst
ret void
}
@@ -1942,82 +1659,29 @@ define void @cmpxchg_i16_monotonic_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounw
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: cmpxchg_i16_monotonic_monotonic:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a3, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a4, 16
-; RV64IA-WMO-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NEXT: sllw a5, a4, a0
-; RV64IA-WMO-NEXT: and a1, a1, a4
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: and a2, a2, a4
-; RV64IA-WMO-NEXT: sllw a0, a2, a0
-; RV64IA-WMO-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a2, (a3)
-; RV64IA-WMO-NEXT: and a4, a2, a5
-; RV64IA-WMO-NEXT: bne a4, a1, .LBB10_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
-; RV64IA-WMO-NEXT: xor a4, a2, a0
-; RV64IA-WMO-NEXT: and a4, a4, a5
-; RV64IA-WMO-NEXT: xor a4, a2, a4
-; RV64IA-WMO-NEXT: sc.w a4, a4, (a3)
-; RV64IA-WMO-NEXT: bnez a4, .LBB10_1
-; RV64IA-WMO-NEXT: .LBB10_3:
-; RV64IA-WMO-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: cmpxchg_i16_monotonic_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a3, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a4, 16
-; RV64IA-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-ZACAS-NEXT: sllw a5, a4, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a4
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: and a2, a2, a4
-; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
-; RV64IA-ZACAS-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a2, (a3)
-; RV64IA-ZACAS-NEXT: and a4, a2, a5
-; RV64IA-ZACAS-NEXT: bne a4, a1, .LBB10_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a4, a2, a0
-; RV64IA-ZACAS-NEXT: and a4, a4, a5
-; RV64IA-ZACAS-NEXT: xor a4, a2, a4
-; RV64IA-ZACAS-NEXT: sc.w a4, a4, (a3)
-; RV64IA-ZACAS-NEXT: bnez a4, .LBB10_1
-; RV64IA-ZACAS-NEXT: .LBB10_3:
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-ZABHA-LABEL: cmpxchg_i16_monotonic_monotonic:
-; RV64IA-ZABHA: # %bb.0:
-; RV64IA-ZABHA-NEXT: amocas.h a1, a2, (a0)
-; RV64IA-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-LABEL: cmpxchg_i16_monotonic_monotonic:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a3, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a4, 16
-; RV64IA-TSO-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NEXT: sllw a5, a4, a0
-; RV64IA-TSO-NEXT: and a1, a1, a4
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: and a2, a2, a4
-; RV64IA-TSO-NEXT: sllw a0, a2, a0
-; RV64IA-TSO-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a2, (a3)
-; RV64IA-TSO-NEXT: and a4, a2, a5
-; RV64IA-TSO-NEXT: bne a4, a1, .LBB10_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
-; RV64IA-TSO-NEXT: xor a4, a2, a0
-; RV64IA-TSO-NEXT: and a4, a4, a5
-; RV64IA-TSO-NEXT: xor a4, a2, a4
-; RV64IA-TSO-NEXT: sc.w a4, a4, (a3)
-; RV64IA-TSO-NEXT: bnez a4, .LBB10_1
-; RV64IA-TSO-NEXT: .LBB10_3:
-; RV64IA-TSO-NEXT: ret
+; RV64IA-LABEL: cmpxchg_i16_monotonic_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addi a4, a4, -1
+; RV64IA-NEXT: sllw a5, a4, a0
+; RV64IA-NEXT: and a1, a1, a4
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: and a2, a2, a4
+; RV64IA-NEXT: sllw a0, a2, a0
+; RV64IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a2, (a3)
+; RV64IA-NEXT: and a4, a2, a5
+; RV64IA-NEXT: bne a4, a1, .LBB10_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
+; RV64IA-NEXT: xor a4, a2, a0
+; RV64IA-NEXT: and a4, a4, a5
+; RV64IA-NEXT: xor a4, a2, a4
+; RV64IA-NEXT: sc.w a4, a4, (a3)
+; RV64IA-NEXT: bnez a4, .LBB10_1
+; RV64IA-NEXT: .LBB10_3:
+; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val monotonic monotonic
ret void
}
@@ -2193,11 +1857,6 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: .LBB11_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_acquire_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.h.aq a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i16_acquire_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -2245,11 +1904,6 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB11_1
; RV64IA-TSO-ZACAS-NEXT: .LBB11_3:
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_acquire_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire monotonic
ret void
}
@@ -2425,11 +2079,6 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: .LBB12_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_acquire_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.h.aq a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i16_acquire_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -2477,11 +2126,6 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB12_1
; RV64IA-TSO-ZACAS-NEXT: .LBB12_3:
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_acquire_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire acquire
ret void
}
@@ -2657,11 +2301,6 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: .LBB13_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_release_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.h.rl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i16_release_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -2709,11 +2348,6 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB13_1
; RV64IA-TSO-ZACAS-NEXT: .LBB13_3:
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_release_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release monotonic
ret void
}
@@ -2889,11 +2523,6 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: .LBB14_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_release_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.h.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i16_release_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -2941,11 +2570,6 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB14_1
; RV64IA-TSO-ZACAS-NEXT: .LBB14_3:
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_release_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release acquire
ret void
}
@@ -3121,11 +2745,6 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: .LBB15_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_acq_rel_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.h.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -3173,11 +2792,6 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB15_1
; RV64IA-TSO-ZACAS-NEXT: .LBB15_3:
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_acq_rel_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel monotonic
ret void
}
@@ -3353,11 +2967,6 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: .LBB16_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_acq_rel_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.h.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -3405,11 +3014,6 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB16_1
; RV64IA-TSO-ZACAS-NEXT: .LBB16_3:
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_acq_rel_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel acquire
ret void
}
@@ -3465,87 +3069,29 @@ define void @cmpxchg_i16_seq_cst_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: cmpxchg_i16_seq_cst_monotonic:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a3, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a4, 16
-; RV64IA-WMO-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NEXT: sllw a5, a4, a0
-; RV64IA-WMO-NEXT: and a1, a1, a4
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: and a2, a2, a4
-; RV64IA-WMO-NEXT: sllw a0, a2, a0
-; RV64IA-WMO-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-WMO-NEXT: and a4, a2, a5
-; RV64IA-WMO-NEXT: bne a4, a1, .LBB17_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
-; RV64IA-WMO-NEXT: xor a4, a2, a0
-; RV64IA-WMO-NEXT: and a4, a4, a5
-; RV64IA-WMO-NEXT: xor a4, a2, a4
-; RV64IA-WMO-NEXT: sc.w.rl a4, a4, (a3)
-; RV64IA-WMO-NEXT: bnez a4, .LBB17_1
-; RV64IA-WMO-NEXT: .LBB17_3:
-; RV64IA-WMO-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: cmpxchg_i16_seq_cst_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a3, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a4, 16
-; RV64IA-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-ZACAS-NEXT: sllw a5, a4, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a4
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: and a2, a2, a4
-; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
-; RV64IA-ZACAS-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-ZACAS-NEXT: and a4, a2, a5
-; RV64IA-ZACAS-NEXT: bne a4, a1, .LBB17_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a4, a2, a0
-; RV64IA-ZACAS-NEXT: and a4, a4, a5
-; RV64IA-ZACAS-NEXT: xor a4, a2, a4
-; RV64IA-ZACAS-NEXT: sc.w.rl a4, a4, (a3)
-; RV64IA-ZACAS-NEXT: bnez a4, .LBB17_1
-; RV64IA-ZACAS-NEXT: .LBB17_3:
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_seq_cst_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.h.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-LABEL: cmpxchg_i16_seq_cst_monotonic:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a3, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a4, 16
-; RV64IA-TSO-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NEXT: sllw a5, a4, a0
-; RV64IA-TSO-NEXT: and a1, a1, a4
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: and a2, a2, a4
-; RV64IA-TSO-NEXT: sllw a0, a2, a0
-; RV64IA-TSO-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-TSO-NEXT: and a4, a2, a5
-; RV64IA-TSO-NEXT: bne a4, a1, .LBB17_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
-; RV64IA-TSO-NEXT: xor a4, a2, a0
-; RV64IA-TSO-NEXT: and a4, a4, a5
-; RV64IA-TSO-NEXT: xor a4, a2, a4
-; RV64IA-TSO-NEXT: sc.w.rl a4, a4, (a3)
-; RV64IA-TSO-NEXT: bnez a4, .LBB17_1
-; RV64IA-TSO-NEXT: .LBB17_3:
-; RV64IA-TSO-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_seq_cst_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: cmpxchg_i16_seq_cst_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addi a4, a4, -1
+; RV64IA-NEXT: sllw a5, a4, a0
+; RV64IA-NEXT: and a1, a1, a4
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: and a2, a2, a4
+; RV64IA-NEXT: sllw a0, a2, a0
+; RV64IA-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-NEXT: and a4, a2, a5
+; RV64IA-NEXT: bne a4, a1, .LBB17_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
+; RV64IA-NEXT: xor a4, a2, a0
+; RV64IA-NEXT: and a4, a4, a5
+; RV64IA-NEXT: xor a4, a2, a4
+; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-NEXT: bnez a4, .LBB17_1
+; RV64IA-NEXT: .LBB17_3:
+; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst monotonic
ret void
}
@@ -3601,87 +3147,29 @@ define void @cmpxchg_i16_seq_cst_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: cmpxchg_i16_seq_cst_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a3, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a4, 16
-; RV64IA-WMO-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NEXT: sllw a5, a4, a0
-; RV64IA-WMO-NEXT: and a1, a1, a4
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: and a2, a2, a4
-; RV64IA-WMO-NEXT: sllw a0, a2, a0
-; RV64IA-WMO-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-WMO-NEXT: and a4, a2, a5
-; RV64IA-WMO-NEXT: bne a4, a1, .LBB18_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
-; RV64IA-WMO-NEXT: xor a4, a2, a0
-; RV64IA-WMO-NEXT: and a4, a4, a5
-; RV64IA-WMO-NEXT: xor a4, a2, a4
-; RV64IA-WMO-NEXT: sc.w.rl a4, a4, (a3)
-; RV64IA-WMO-NEXT: bnez a4, .LBB18_1
-; RV64IA-WMO-NEXT: .LBB18_3:
-; RV64IA-WMO-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: cmpxchg_i16_seq_cst_acquire:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a3, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a4, 16
-; RV64IA-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-ZACAS-NEXT: sllw a5, a4, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a4
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: and a2, a2, a4
-; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
-; RV64IA-ZACAS-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-ZACAS-NEXT: and a4, a2, a5
-; RV64IA-ZACAS-NEXT: bne a4, a1, .LBB18_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a4, a2, a0
-; RV64IA-ZACAS-NEXT: and a4, a4, a5
-; RV64IA-ZACAS-NEXT: xor a4, a2, a4
-; RV64IA-ZACAS-NEXT: sc.w.rl a4, a4, (a3)
-; RV64IA-ZACAS-NEXT: bnez a4, .LBB18_1
-; RV64IA-ZACAS-NEXT: .LBB18_3:
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_seq_cst_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.h.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-LABEL: cmpxchg_i16_seq_cst_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a3, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a4, 16
-; RV64IA-TSO-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NEXT: sllw a5, a4, a0
-; RV64IA-TSO-NEXT: and a1, a1, a4
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: and a2, a2, a4
-; RV64IA-TSO-NEXT: sllw a0, a2, a0
-; RV64IA-TSO-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-TSO-NEXT: and a4, a2, a5
-; RV64IA-TSO-NEXT: bne a4, a1, .LBB18_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
-; RV64IA-TSO-NEXT: xor a4, a2, a0
-; RV64IA-TSO-NEXT: and a4, a4, a5
-; RV64IA-TSO-NEXT: xor a4, a2, a4
-; RV64IA-TSO-NEXT: sc.w.rl a4, a4, (a3)
-; RV64IA-TSO-NEXT: bnez a4, .LBB18_1
-; RV64IA-TSO-NEXT: .LBB18_3:
-; RV64IA-TSO-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_seq_cst_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: cmpxchg_i16_seq_cst_acquire:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addi a4, a4, -1
+; RV64IA-NEXT: sllw a5, a4, a0
+; RV64IA-NEXT: and a1, a1, a4
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: and a2, a2, a4
+; RV64IA-NEXT: sllw a0, a2, a0
+; RV64IA-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-NEXT: and a4, a2, a5
+; RV64IA-NEXT: bne a4, a1, .LBB18_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
+; RV64IA-NEXT: xor a4, a2, a0
+; RV64IA-NEXT: and a4, a4, a5
+; RV64IA-NEXT: xor a4, a2, a4
+; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-NEXT: bnez a4, .LBB18_1
+; RV64IA-NEXT: .LBB18_3:
+; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst acquire
ret void
}
@@ -3737,87 +3225,29 @@ define void @cmpxchg_i16_seq_cst_seq_cst(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: cmpxchg_i16_seq_cst_seq_cst:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a3, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a4, 16
-; RV64IA-WMO-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NEXT: sllw a5, a4, a0
-; RV64IA-WMO-NEXT: and a1, a1, a4
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: and a2, a2, a4
-; RV64IA-WMO-NEXT: sllw a0, a2, a0
-; RV64IA-WMO-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-WMO-NEXT: and a4, a2, a5
-; RV64IA-WMO-NEXT: bne a4, a1, .LBB19_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
-; RV64IA-WMO-NEXT: xor a4, a2, a0
-; RV64IA-WMO-NEXT: and a4, a4, a5
-; RV64IA-WMO-NEXT: xor a4, a2, a4
-; RV64IA-WMO-NEXT: sc.w.rl a4, a4, (a3)
-; RV64IA-WMO-NEXT: bnez a4, .LBB19_1
-; RV64IA-WMO-NEXT: .LBB19_3:
-; RV64IA-WMO-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: cmpxchg_i16_seq_cst_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a3, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a4, 16
-; RV64IA-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-ZACAS-NEXT: sllw a5, a4, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a4
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: and a2, a2, a4
-; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
-; RV64IA-ZACAS-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-ZACAS-NEXT: and a4, a2, a5
-; RV64IA-ZACAS-NEXT: bne a4, a1, .LBB19_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a4, a2, a0
-; RV64IA-ZACAS-NEXT: and a4, a4, a5
-; RV64IA-ZACAS-NEXT: xor a4, a2, a4
-; RV64IA-ZACAS-NEXT: sc.w.rl a4, a4, (a3)
-; RV64IA-ZACAS-NEXT: bnez a4, .LBB19_1
-; RV64IA-ZACAS-NEXT: .LBB19_3:
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.h.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-LABEL: cmpxchg_i16_seq_cst_seq_cst:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a3, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a4, 16
-; RV64IA-TSO-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NEXT: sllw a5, a4, a0
-; RV64IA-TSO-NEXT: and a1, a1, a4
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: and a2, a2, a4
-; RV64IA-TSO-NEXT: sllw a0, a2, a0
-; RV64IA-TSO-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-TSO-NEXT: and a4, a2, a5
-; RV64IA-TSO-NEXT: bne a4, a1, .LBB19_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
-; RV64IA-TSO-NEXT: xor a4, a2, a0
-; RV64IA-TSO-NEXT: and a4, a4, a5
-; RV64IA-TSO-NEXT: xor a4, a2, a4
-; RV64IA-TSO-NEXT: sc.w.rl a4, a4, (a3)
-; RV64IA-TSO-NEXT: bnez a4, .LBB19_1
-; RV64IA-TSO-NEXT: .LBB19_3:
-; RV64IA-TSO-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a3, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addi a4, a4, -1
+; RV64IA-NEXT: sllw a5, a4, a0
+; RV64IA-NEXT: and a1, a1, a4
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: and a2, a2, a4
+; RV64IA-NEXT: sllw a0, a2, a0
+; RV64IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-NEXT: and a4, a2, a5
+; RV64IA-NEXT: bne a4, a1, .LBB19_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
+; RV64IA-NEXT: xor a4, a2, a0
+; RV64IA-NEXT: and a4, a4, a5
+; RV64IA-NEXT: xor a4, a2, a4
+; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-NEXT: bnez a4, .LBB19_1
+; RV64IA-NEXT: .LBB19_3:
+; RV64IA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst seq_cst
ret void
}
@@ -3893,11 +3323,6 @@ define void @cmpxchg_i32_monotonic_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounw
; RV64IA-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-ZACAS-NEXT: ret
;
-; RV64IA-ZABHA-LABEL: cmpxchg_i32_monotonic_monotonic:
-; RV64IA-ZABHA: # %bb.0:
-; RV64IA-ZABHA-NEXT: amocas.w a1, a2, (a0)
-; RV64IA-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i32_monotonic_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -3989,11 +3414,6 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aq a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_acquire_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.w.aq a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i32_acquire_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -4010,11 +3430,6 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_acquire_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acquire monotonic
ret void
}
@@ -4095,11 +3510,6 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aq a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_acquire_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.w.aq a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i32_acquire_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -4116,11 +3526,6 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_acquire_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acquire acquire
ret void
}
@@ -4201,11 +3606,6 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.w.rl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_release_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.w.rl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i32_release_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -4222,11 +3622,6 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_release_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release monotonic
ret void
}
@@ -4307,11 +3702,6 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_release_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.w.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i32_release_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -4328,11 +3718,6 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_release_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release acquire
ret void
}
@@ -4413,11 +3798,6 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_acq_rel_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.w.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i32_acq_rel_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -4434,11 +3814,6 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_acq_rel_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel monotonic
ret void
}
@@ -4519,11 +3894,6 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_acq_rel_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.w.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i32_acq_rel_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -4540,11 +3910,6 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_acq_rel_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel acquire
ret void
}
@@ -4625,11 +3990,6 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_seq_cst_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.w.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -4646,11 +4006,6 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_seq_cst_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst monotonic
ret void
}
@@ -4731,11 +4086,6 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_seq_cst_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.w.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -4752,11 +4102,6 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_seq_cst_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst acquire
ret void
}
@@ -4837,11 +4182,6 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.w.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -4858,11 +4198,6 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst
ret void
}
@@ -4929,11 +4264,6 @@ define void @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounw
; RV64IA-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-ZACAS-NEXT: ret
;
-; RV64IA-ZABHA-LABEL: cmpxchg_i64_monotonic_monotonic:
-; RV64IA-ZABHA: # %bb.0:
-; RV64IA-ZABHA-NEXT: amocas.d a1, a2, (a0)
-; RV64IA-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i64_monotonic_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
@@ -5012,11 +4342,6 @@ define void @cmpxchg_i64_acquire_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aq a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_acquire_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.d.aq a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i64_acquire_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
@@ -5032,11 +4357,6 @@ define void @cmpxchg_i64_acquire_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_acquire_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acquire monotonic
ret void
}
@@ -5105,11 +4425,6 @@ define void @cmpxchg_i64_acquire_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aq a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_acquire_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.d.aq a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i64_acquire_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
@@ -5125,11 +4440,6 @@ define void @cmpxchg_i64_acquire_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_acquire_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acquire acquire
ret void
}
@@ -5198,11 +4508,6 @@ define void @cmpxchg_i64_release_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.d.rl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_release_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.d.rl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i64_release_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
@@ -5218,11 +4523,6 @@ define void @cmpxchg_i64_release_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_release_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val release monotonic
ret void
}
@@ -5291,11 +4591,6 @@ define void @cmpxchg_i64_release_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_release_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.d.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i64_release_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
@@ -5311,11 +4606,6 @@ define void @cmpxchg_i64_release_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_release_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val release acquire
ret void
}
@@ -5384,11 +4674,6 @@ define void @cmpxchg_i64_acq_rel_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_acq_rel_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.d.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i64_acq_rel_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
@@ -5404,11 +4689,6 @@ define void @cmpxchg_i64_acq_rel_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_acq_rel_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acq_rel monotonic
ret void
}
@@ -5477,11 +4757,6 @@ define void @cmpxchg_i64_acq_rel_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_acq_rel_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.d.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i64_acq_rel_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
@@ -5497,11 +4772,6 @@ define void @cmpxchg_i64_acq_rel_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_acq_rel_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acq_rel acquire
ret void
}
@@ -5570,11 +4840,6 @@ define void @cmpxchg_i64_seq_cst_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_seq_cst_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.d.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i64_seq_cst_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
@@ -5590,11 +4855,6 @@ define void @cmpxchg_i64_seq_cst_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_seq_cst_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst monotonic
ret void
}
@@ -5663,11 +4923,6 @@ define void @cmpxchg_i64_seq_cst_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_seq_cst_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.d.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i64_seq_cst_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
@@ -5683,11 +4938,6 @@ define void @cmpxchg_i64_seq_cst_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_seq_cst_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst acquire
ret void
}
@@ -5756,11 +5006,6 @@ define void @cmpxchg_i64_seq_cst_seq_cst(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amocas.d.aqrl a1, a2, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
; RV64IA-TSO-LABEL: cmpxchg_i64_seq_cst_seq_cst:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
@@ -5776,13 +5021,6 @@ define void @cmpxchg_i64_seq_cst_seq_cst(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst seq_cst
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; RV64IA: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index ee802507a02f3c..62206a6a2ece53 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -21,15 +21,6 @@
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+experimental-zacas -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-TSO,RV64IA-TSO-ZACAS %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zabha -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO,RV64IA-WMO-ZABHA,RV64IA-WMO-ZABHA-NOZACAS %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+experimental-zabha -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO,RV64IA-TSO-ZABHA,RV64IA-TSO-ZABHA-NOZACAS %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zabha,+experimental-zacas -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO,RV64IA-WMO-ZABHA,RV64IA-WMO-ZABHA-ZACAS %s
-; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+experimental-zabha,+experimental-zacas -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO,RV64IA-TSO-ZABHA,RV64IA-TSO-ZABHA-ZACAS %s
-
define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_monotonic:
; RV32I: # %bb.0:
@@ -71,55 +62,25 @@ define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i8_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a3, 255
-; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-NOZACAS-NEXT: mv a5, a1
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB0_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_xchg_i8_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a3, 255
-; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-ZACAS-NEXT: mv a5, a1
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB0_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_xchg_i8_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a3, 255
+; RV64IA-NEXT: sllw a3, a3, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a4, (a2)
+; RV64IA-NEXT: mv a5, a1
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB0_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a4, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -185,95 +146,45 @@ define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB1_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i8_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB1_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i8_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB1_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i8_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB1_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NEXT: mv a5, a1
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB1_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: mv a5, a1
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB1_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 %b acquire
ret i8 %1
}
@@ -339,95 +250,45 @@ define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB2_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i8_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB2_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i8_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB2_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i8_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB2_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-NEXT: mv a5, a1
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB2_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: mv a5, a1
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB2_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 %b release
ret i8 %1
}
@@ -493,95 +354,45 @@ define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB3_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i8_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB3_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i8_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB3_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i8_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB3_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NEXT: mv a5, a1
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB3_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: mv a5, a1
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB3_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -627,55 +438,25 @@ define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i8_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a3, 255
-; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-NOZACAS-NEXT: mv a5, a1
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB4_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_xchg_i8_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a3, 255
-; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-ZACAS-NEXT: mv a5, a1
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB4_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_xchg_i8_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a3, 255
+; RV64IA-NEXT: sllw a3, a3, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-NEXT: mv a5, a1
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB4_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a4, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -717,37 +498,16 @@ define i8 @atomicrmw_xchg_0_i8_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_0_i8_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a2, 255
-; RV64IA-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-NOZACAS-NEXT: not a2, a2
-; RV64IA-NOZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_xchg_0_i8_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a2, 255
-; RV64IA-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-ZACAS-NEXT: not a2, a2
-; RV64IA-ZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b a0, zero, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_xchg_0_i8_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a1, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a2, 255
+; RV64IA-NEXT: sllw a2, a2, a0
+; RV64IA-NEXT: not a2, a2
+; RV64IA-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-NEXT: srlw a0, a1, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 monotonic
ret i8 %1
}
@@ -797,59 +557,27 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aq a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a2, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: not a2, a2
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.aq a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i8_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a2, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: not a2, a2
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aq a0, zero, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aq a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 acquire
ret i8 %1
}
@@ -899,59 +627,27 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.rl a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a2, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: not a2, a2
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.rl a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i8_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a2, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: not a2, a2
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b.rl a0, zero, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.rl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 release
ret i8 %1
}
@@ -1001,59 +697,27 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a2, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: not a2, a2
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a2, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: not a2, a2
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, zero, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 acq_rel
ret i8 %1
}
@@ -1103,59 +767,27 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a2, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: not a2, a2
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a2, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: not a2, a2
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, zero, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 seq_cst
ret i8 %1
}
@@ -1193,37 +825,15 @@ define i8 @atomicrmw_xchg_minus_1_i8_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a2, 255
-; RV64IA-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-NOZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a2, 255
-; RV64IA-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-ZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: li a1, -1
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: li a1, -1
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_xchg_minus_1_i8_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a1, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a2, 255
+; RV64IA-NEXT: sllw a2, a2, a0
+; RV64IA-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-NEXT: srlw a0, a1, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 monotonic
ret i8 %1
}
@@ -1271,57 +881,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aq a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a2, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.aq a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a2, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.aq a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: li a1, -1
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: li a1, -1
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 acquire
ret i8 %1
}
@@ -1369,57 +947,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.rl a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a2, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.rl a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a2, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.rl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: li a1, -1
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: li a1, -1
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 release
ret i8 %1
}
@@ -1467,57 +1013,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a2, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a2, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: li a1, -1
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: li a1, -1
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 acq_rel
ret i8 %1
}
@@ -1565,57 +1079,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a2, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a2, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: li a1, -1
-; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: li a1, -1
-; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 seq_cst
ret i8 %1
}
@@ -1661,55 +1143,25 @@ define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_add_i8_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a3, 255
-; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-NOZACAS-NEXT: add a5, a4, a1
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB15_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_add_i8_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a3, 255
-; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-ZACAS-NEXT: add a5, a4, a1
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB15_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_add_i8_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a3, 255
+; RV64IA-NEXT: sllw a3, a3, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a4, (a2)
+; RV64IA-NEXT: add a5, a4, a1
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB15_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a4, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw add ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -1775,95 +1227,45 @@ define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: add a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB16_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_add_i8_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: add a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB16_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i8_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: add a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB16_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_add_i8_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: add a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB16_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_add_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NEXT: add a5, a4, a1
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB16_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_add_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: add a5, a4, a1
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB16_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw add ptr %a, i8 %b acquire
ret i8 %1
}
@@ -1929,95 +1331,45 @@ define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: add a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB17_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_add_i8_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: add a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB17_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i8_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: add a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB17_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_add_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-NEXT: add a5, a4, a1
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB17_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_add_i8_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: add a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB17_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoadd.b.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_add_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: add a5, a4, a1
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB17_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw add ptr %a, i8 %b release
ret i8 %1
}
@@ -2083,95 +1435,45 @@ define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: add a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB18_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_add_i8_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: add a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB18_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i8_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: add a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB18_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_add_i8_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: add a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB18_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_add_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NEXT: add a5, a4, a1
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB18_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_add_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: add a5, a4, a1
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB18_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw add ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -2217,55 +1519,25 @@ define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_add_i8_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a3, 255
-; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-NOZACAS-NEXT: add a5, a4, a1
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB19_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_add_i8_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a3, 255
-; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-ZACAS-NEXT: add a5, a4, a1
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB19_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_add_i8_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a3, 255
+; RV64IA-NEXT: sllw a3, a3, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-NEXT: add a5, a4, a1
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB19_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a4, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw add ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -2311,57 +1583,25 @@ define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i8_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a3, 255
-; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-NOZACAS-NEXT: sub a5, a4, a1
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB20_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_sub_i8_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a3, 255
-; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-ZACAS-NEXT: sub a5, a4, a1
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB20_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
-; RV64IA-WMO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
-; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_sub_i8_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a3, 255
+; RV64IA-NEXT: sllw a3, a3, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a4, (a2)
+; RV64IA-NEXT: sub a5, a4, a1
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB20_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a4, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw sub ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -2427,97 +1667,45 @@ define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: sub a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB21_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i8_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: sub a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB21_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i8_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: sub a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB21_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_sub_i8_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: sub a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB21_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_sub_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NEXT: sub a5, a4, a1
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB21_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
-; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
-; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_sub_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: sub a5, a4, a1
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB21_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw sub ptr %a, i8 %b acquire
ret i8 %1
}
@@ -2583,97 +1771,45 @@ define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: sub a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB22_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i8_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: sub a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB22_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i8_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: sub a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB22_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_sub_i8_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: sub a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB22_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_sub_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-NEXT: sub a5, a4, a1
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB22_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
-; RV64IA-WMO-ZABHA-NEXT: amoadd.b.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
-; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_sub_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: sub a5, a4, a1
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB22_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw sub ptr %a, i8 %b release
ret i8 %1
}
@@ -2739,97 +1875,45 @@ define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: sub a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB23_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i8_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: sub a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB23_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i8_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: sub a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB23_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_sub_i8_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: sub a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB23_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_sub_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NEXT: sub a5, a4, a1
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB23_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
-; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
-; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_sub_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: sub a5, a4, a1
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB23_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw sub ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -2875,57 +1959,25 @@ define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i8_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a3, 255
-; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-NOZACAS-NEXT: sub a5, a4, a1
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB24_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_sub_i8_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a3, 255
-; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-ZACAS-NEXT: sub a5, a4, a1
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB24_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
-; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
-; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_sub_i8_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a3, 255
+; RV64IA-NEXT: sllw a3, a3, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-NEXT: sub a5, a4, a1
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB24_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a4, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw sub ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -2965,43 +2017,19 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_and_i8_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a3, 255
-; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-NOZACAS-NEXT: not a3, a3
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: or a1, a3, a1
-; RV64IA-NOZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_and_i8_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a3, 255
-; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-ZACAS-NEXT: not a3, a3
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: or a1, a3, a1
-; RV64IA-ZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoand.b a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_and_i8_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a3, 255
+; RV64IA-NEXT: sllw a3, a3, a0
+; RV64IA-NEXT: not a3, a3
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: or a1, a3, a1
+; RV64IA-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-NEXT: srlw a0, a1, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -3055,71 +2083,33 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a3, a3
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aq a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i8_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a3, a3
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.aq a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i8_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoand.b.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: not a3, a3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a3, a1
+; RV64IA-WMO-NEXT: amoand.w.aq a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_and_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: not a3, a3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a3, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b acquire
ret i8 %1
}
@@ -3173,71 +2163,33 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a3, a3
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.rl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i8_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a3, a3
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.rl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i8_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoand.b.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: not a3, a3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a3, a1
+; RV64IA-WMO-NEXT: amoand.w.rl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_and_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: not a3, a3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a3, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b release
ret i8 %1
}
@@ -3291,71 +2243,33 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a3, a3
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i8_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a3, a3
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i8_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoand.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: not a3, a3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a3, a1
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_and_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: not a3, a3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a3, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -3409,71 +2323,33 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_seq_cst:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a3, a3
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i8_seq_cst:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a3, a3
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_seq_cst:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i8_seq_cst:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoand.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i8_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: not a3, a3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a3, a1
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_and_i8_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: not a3, a3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a3, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -3520,119 +2396,26 @@ define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i8_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a3, 255
-; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-NOZACAS-NEXT: not a5, a5
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB30_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_nand_i8_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a3, 255
-; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-ZACAS-NEXT: and a5, a4, a1
-; RV64IA-ZACAS-NEXT: not a5, a5
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB30_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_monotonic:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB30_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_monotonic:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB30_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_monotonic:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB30_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB30_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_monotonic:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB30_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB30_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
+; RV64IA-LABEL: atomicrmw_nand_i8_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a3, 255
+; RV64IA-NEXT: sllw a3, a3, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a4, (a2)
+; RV64IA-NEXT: and a5, a4, a1
+; RV64IA-NEXT: not a5, a5
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB30_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a4, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw nand ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -3700,161 +2483,47 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB31_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i8_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB31_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i8_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB31_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_nand_i8_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB31_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_nand_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NEXT: and a5, a4, a1
+; RV64IA-WMO-NEXT: not a5, a5
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB31_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_acquire:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB31_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_acquire:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB31_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_acquire:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB31_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.b.aq a0, a3, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB31_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_acquire:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB31_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB31_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_nand_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: and a5, a4, a1
+; RV64IA-TSO-NEXT: not a5, a5
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB31_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw nand ptr %a, i8 %b acquire
ret i8 %1
}
@@ -3922,161 +2591,47 @@ define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB32_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i8_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB32_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i8_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB32_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_nand_i8_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB32_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_nand_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-NEXT: and a5, a4, a1
+; RV64IA-WMO-NEXT: not a5, a5
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB32_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_release:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB32_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_release:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB32_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_release:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB32_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.b.rl a0, a3, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB32_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_release:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB32_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB32_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_nand_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: and a5, a4, a1
+; RV64IA-TSO-NEXT: not a5, a5
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB32_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw nand ptr %a, i8 %b release
ret i8 %1
}
@@ -4144,161 +2699,47 @@ define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB33_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB33_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB33_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB33_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_nand_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NEXT: and a5, a4, a1
+; RV64IA-WMO-NEXT: not a5, a5
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB33_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB33_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB33_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB33_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.b.aqrl a0, a3, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB33_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB33_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB33_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_nand_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: and a5, a4, a1
+; RV64IA-TSO-NEXT: not a5, a5
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB33_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw nand ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -4345,119 +2786,26 @@ define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i8_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a3, 255
-; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-NOZACAS-NEXT: not a5, a5
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB34_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_nand_i8_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a3, 255
-; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-ZACAS-NEXT: and a5, a4, a1
-; RV64IA-ZACAS-NEXT: not a5, a5
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB34_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_seq_cst:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB34_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_seq_cst:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB34_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_seq_cst:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB34_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.b.aqrl a0, a3, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB34_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_seq_cst:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB34_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB34_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
+; RV64IA-LABEL: atomicrmw_nand_i8_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a3, 255
+; RV64IA-NEXT: sllw a3, a3, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-NEXT: and a5, a4, a1
+; RV64IA-NEXT: not a5, a5
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB34_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a4, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw nand ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -4493,35 +2841,15 @@ define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_or_i8_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_or_i8_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoor.b a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_or_i8_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-NEXT: srlw a0, a1, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -4567,55 +2895,25 @@ define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aq a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i8_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.aq a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i8_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoor.b.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.aq a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_or_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b acquire
ret i8 %1
}
@@ -4661,55 +2959,25 @@ define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.rl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i8_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.rl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i8_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoor.b.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.rl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_or_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b release
ret i8 %1
}
@@ -4755,55 +3023,25 @@ define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i8_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i8_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoor.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_or_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -4849,55 +3087,25 @@ define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_seq_cst:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i8_seq_cst:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_seq_cst:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i8_seq_cst:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoor.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i8_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_or_i8_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -4933,35 +3141,15 @@ define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_xor_i8_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_xor_i8_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoxor.b a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_xor_i8_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-NEXT: srlw a0, a1, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -5007,55 +3195,25 @@ define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.aq a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i8_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoxor.w.aq a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i8_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoxor.b.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.aq a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xor_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b acquire
ret i8 %1
}
@@ -5101,55 +3259,25 @@ define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.rl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i8_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoxor.w.rl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i8_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoxor.b.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.rl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xor_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b release
ret i8 %1
}
@@ -5195,55 +3323,25 @@ define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i8_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i8_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoxor.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -5289,55 +3387,25 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_seq_cst:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i8_seq_cst:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_seq_cst:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i8_seq_cst:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoxor.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -5456,73 +3524,34 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_max_i8_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-NOZACAS-NEXT: li a4, 255
-; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-NOZACAS-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-NOZACAS-NEXT: mv a6, a5
-; RV64IA-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-NOZACAS-NEXT: bge a7, a1, .LBB45_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-NOZACAS-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a6, .LBB45_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_max_i8_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-ZACAS-NEXT: li a4, 255
-; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-ZACAS-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-ZACAS-NEXT: mv a6, a5
-; RV64IA-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-ZACAS-NEXT: bge a7, a1, .LBB45_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-ZACAS-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-ZACAS-NEXT: bnez a6, .LBB45_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomax.b a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_max_i8_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: li a4, 255
+; RV64IA-NEXT: sllw a4, a4, a0
+; RV64IA-NEXT: slli a1, a1, 56
+; RV64IA-NEXT: srai a1, a1, 56
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: xori a3, a3, 56
+; RV64IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a5, (a2)
+; RV64IA-NEXT: and a7, a5, a4
+; RV64IA-NEXT: mv a6, a5
+; RV64IA-NEXT: sll a7, a7, a3
+; RV64IA-NEXT: sra a7, a7, a3
+; RV64IA-NEXT: bge a7, a1, .LBB45_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1
+; RV64IA-NEXT: xor a6, a5, a1
+; RV64IA-NEXT: and a6, a6, a4
+; RV64IA-NEXT: xor a6, a5, a6
+; RV64IA-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1
+; RV64IA-NEXT: sc.w a6, a6, (a2)
+; RV64IA-NEXT: bnez a6, .LBB45_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a5, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -5670,131 +3699,63 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NOZACAS-NEXT: li a4, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-WMO-NOZACAS-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a6, a5
-; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB46_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-WMO-NOZACAS-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB46_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_max_i8_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NOZACAS-NEXT: li a4, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-TSO-NOZACAS-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a6, a5
-; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB46_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-TSO-NOZACAS-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB46_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i8_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-ZACAS-NEXT: li a4, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-WMO-ZACAS-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a6, a5
-; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB46_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-WMO-ZACAS-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB46_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_max_i8_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-ZACAS-NEXT: li a4, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-TSO-ZACAS-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a6, a5
-; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB46_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-TSO-ZACAS-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB46_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomax.b.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_max_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NEXT: li a4, 255
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: slli a1, a1, 56
+; RV64IA-WMO-NEXT: srai a1, a1, 56
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: xori a3, a3, 56
+; RV64IA-WMO-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a5, (a2)
+; RV64IA-WMO-NEXT: and a7, a5, a4
+; RV64IA-WMO-NEXT: mv a6, a5
+; RV64IA-WMO-NEXT: sll a7, a7, a3
+; RV64IA-WMO-NEXT: sra a7, a7, a3
+; RV64IA-WMO-NEXT: bge a7, a1, .LBB46_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
+; RV64IA-WMO-NEXT: xor a6, a5, a1
+; RV64IA-WMO-NEXT: and a6, a6, a4
+; RV64IA-WMO-NEXT: xor a6, a5, a6
+; RV64IA-WMO-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-WMO-NEXT: bnez a6, .LBB46_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_max_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NEXT: li a4, 255
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: slli a1, a1, 56
+; RV64IA-TSO-NEXT: srai a1, a1, 56
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: xori a3, a3, 56
+; RV64IA-TSO-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-NEXT: and a7, a5, a4
+; RV64IA-TSO-NEXT: mv a6, a5
+; RV64IA-TSO-NEXT: sll a7, a7, a3
+; RV64IA-TSO-NEXT: sra a7, a7, a3
+; RV64IA-TSO-NEXT: bge a7, a1, .LBB46_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
+; RV64IA-TSO-NEXT: xor a6, a5, a1
+; RV64IA-TSO-NEXT: and a6, a6, a4
+; RV64IA-TSO-NEXT: xor a6, a5, a6
+; RV64IA-TSO-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NEXT: bnez a6, .LBB46_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b acquire
ret i8 %1
}
@@ -5942,131 +3903,63 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NOZACAS-NEXT: li a4, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-WMO-NOZACAS-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a6, a5
-; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB47_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-WMO-NOZACAS-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB47_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_max_i8_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NOZACAS-NEXT: li a4, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-TSO-NOZACAS-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a6, a5
-; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB47_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-TSO-NOZACAS-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB47_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i8_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-ZACAS-NEXT: li a4, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-WMO-ZACAS-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a6, a5
-; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB47_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-WMO-ZACAS-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB47_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_max_i8_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-ZACAS-NEXT: li a4, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-TSO-ZACAS-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a6, a5
-; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB47_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-TSO-ZACAS-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB47_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomax.b.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_max_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NEXT: li a4, 255
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: slli a1, a1, 56
+; RV64IA-WMO-NEXT: srai a1, a1, 56
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: xori a3, a3, 56
+; RV64IA-WMO-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a5, (a2)
+; RV64IA-WMO-NEXT: and a7, a5, a4
+; RV64IA-WMO-NEXT: mv a6, a5
+; RV64IA-WMO-NEXT: sll a7, a7, a3
+; RV64IA-WMO-NEXT: sra a7, a7, a3
+; RV64IA-WMO-NEXT: bge a7, a1, .LBB47_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
+; RV64IA-WMO-NEXT: xor a6, a5, a1
+; RV64IA-WMO-NEXT: and a6, a6, a4
+; RV64IA-WMO-NEXT: xor a6, a5, a6
+; RV64IA-WMO-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NEXT: bnez a6, .LBB47_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_max_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NEXT: li a4, 255
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: slli a1, a1, 56
+; RV64IA-TSO-NEXT: srai a1, a1, 56
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: xori a3, a3, 56
+; RV64IA-TSO-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-NEXT: and a7, a5, a4
+; RV64IA-TSO-NEXT: mv a6, a5
+; RV64IA-TSO-NEXT: sll a7, a7, a3
+; RV64IA-TSO-NEXT: sra a7, a7, a3
+; RV64IA-TSO-NEXT: bge a7, a1, .LBB47_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
+; RV64IA-TSO-NEXT: xor a6, a5, a1
+; RV64IA-TSO-NEXT: and a6, a6, a4
+; RV64IA-TSO-NEXT: xor a6, a5, a6
+; RV64IA-TSO-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NEXT: bnez a6, .LBB47_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b release
ret i8 %1
}
@@ -6214,131 +4107,63 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NOZACAS-NEXT: li a4, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-WMO-NOZACAS-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a6, a5
-; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB48_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-WMO-NOZACAS-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB48_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_max_i8_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NOZACAS-NEXT: li a4, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-TSO-NOZACAS-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a6, a5
-; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB48_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-TSO-NOZACAS-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB48_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i8_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-ZACAS-NEXT: li a4, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-WMO-ZACAS-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a6, a5
-; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB48_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-WMO-ZACAS-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB48_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_max_i8_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-ZACAS-NEXT: li a4, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-TSO-ZACAS-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a6, a5
-; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB48_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-TSO-ZACAS-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB48_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomax.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_max_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NEXT: li a4, 255
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: slli a1, a1, 56
+; RV64IA-WMO-NEXT: srai a1, a1, 56
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: xori a3, a3, 56
+; RV64IA-WMO-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a5, (a2)
+; RV64IA-WMO-NEXT: and a7, a5, a4
+; RV64IA-WMO-NEXT: mv a6, a5
+; RV64IA-WMO-NEXT: sll a7, a7, a3
+; RV64IA-WMO-NEXT: sra a7, a7, a3
+; RV64IA-WMO-NEXT: bge a7, a1, .LBB48_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
+; RV64IA-WMO-NEXT: xor a6, a5, a1
+; RV64IA-WMO-NEXT: and a6, a6, a4
+; RV64IA-WMO-NEXT: xor a6, a5, a6
+; RV64IA-WMO-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NEXT: bnez a6, .LBB48_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_max_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NEXT: li a4, 255
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: slli a1, a1, 56
+; RV64IA-TSO-NEXT: srai a1, a1, 56
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: xori a3, a3, 56
+; RV64IA-TSO-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-NEXT: and a7, a5, a4
+; RV64IA-TSO-NEXT: mv a6, a5
+; RV64IA-TSO-NEXT: sll a7, a7, a3
+; RV64IA-TSO-NEXT: sra a7, a7, a3
+; RV64IA-TSO-NEXT: bge a7, a1, .LBB48_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
+; RV64IA-TSO-NEXT: xor a6, a5, a1
+; RV64IA-TSO-NEXT: and a6, a6, a4
+; RV64IA-TSO-NEXT: xor a6, a5, a6
+; RV64IA-TSO-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NEXT: bnez a6, .LBB48_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -6457,73 +4282,34 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_max_i8_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-NOZACAS-NEXT: li a4, 255
-; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-NOZACAS-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a5, (a2)
-; RV64IA-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-NOZACAS-NEXT: mv a6, a5
-; RV64IA-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-NOZACAS-NEXT: bge a7, a1, .LBB49_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-NOZACAS-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a6, .LBB49_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_max_i8_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-ZACAS-NEXT: li a4, 255
-; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-ZACAS-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a5, (a2)
-; RV64IA-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-ZACAS-NEXT: mv a6, a5
-; RV64IA-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-ZACAS-NEXT: bge a7, a1, .LBB49_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-ZACAS-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-ZACAS-NEXT: bnez a6, .LBB49_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomax.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_max_i8_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: li a4, 255
+; RV64IA-NEXT: sllw a4, a4, a0
+; RV64IA-NEXT: slli a1, a1, 56
+; RV64IA-NEXT: srai a1, a1, 56
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: xori a3, a3, 56
+; RV64IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a5, (a2)
+; RV64IA-NEXT: and a7, a5, a4
+; RV64IA-NEXT: mv a6, a5
+; RV64IA-NEXT: sll a7, a7, a3
+; RV64IA-NEXT: sra a7, a7, a3
+; RV64IA-NEXT: bge a7, a1, .LBB49_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
+; RV64IA-NEXT: xor a6, a5, a1
+; RV64IA-NEXT: and a6, a6, a4
+; RV64IA-NEXT: xor a6, a5, a6
+; RV64IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1
+; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-NEXT: bnez a6, .LBB49_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a5, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -6642,73 +4428,34 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_min_i8_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-NOZACAS-NEXT: li a4, 255
-; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-NOZACAS-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-NOZACAS-NEXT: mv a6, a5
-; RV64IA-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-NOZACAS-NEXT: bge a1, a7, .LBB50_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-NOZACAS-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a6, .LBB50_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_min_i8_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-ZACAS-NEXT: li a4, 255
-; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-ZACAS-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-ZACAS-NEXT: mv a6, a5
-; RV64IA-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-ZACAS-NEXT: bge a1, a7, .LBB50_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-ZACAS-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-ZACAS-NEXT: bnez a6, .LBB50_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomin.b a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_min_i8_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: li a4, 255
+; RV64IA-NEXT: sllw a4, a4, a0
+; RV64IA-NEXT: slli a1, a1, 56
+; RV64IA-NEXT: srai a1, a1, 56
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: xori a3, a3, 56
+; RV64IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a5, (a2)
+; RV64IA-NEXT: and a7, a5, a4
+; RV64IA-NEXT: mv a6, a5
+; RV64IA-NEXT: sll a7, a7, a3
+; RV64IA-NEXT: sra a7, a7, a3
+; RV64IA-NEXT: bge a1, a7, .LBB50_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1
+; RV64IA-NEXT: xor a6, a5, a1
+; RV64IA-NEXT: and a6, a6, a4
+; RV64IA-NEXT: xor a6, a5, a6
+; RV64IA-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1
+; RV64IA-NEXT: sc.w a6, a6, (a2)
+; RV64IA-NEXT: bnez a6, .LBB50_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a5, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -6856,131 +4603,63 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NOZACAS-NEXT: li a4, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-WMO-NOZACAS-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a6, a5
-; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB51_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-WMO-NOZACAS-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB51_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_min_i8_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NOZACAS-NEXT: li a4, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-TSO-NOZACAS-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a6, a5
-; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB51_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-TSO-NOZACAS-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB51_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i8_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-ZACAS-NEXT: li a4, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-WMO-ZACAS-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a6, a5
-; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB51_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-WMO-ZACAS-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB51_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_min_i8_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-ZACAS-NEXT: li a4, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-TSO-ZACAS-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a6, a5
-; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB51_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-TSO-ZACAS-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB51_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomin.b.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_min_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NEXT: li a4, 255
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: slli a1, a1, 56
+; RV64IA-WMO-NEXT: srai a1, a1, 56
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: xori a3, a3, 56
+; RV64IA-WMO-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a5, (a2)
+; RV64IA-WMO-NEXT: and a7, a5, a4
+; RV64IA-WMO-NEXT: mv a6, a5
+; RV64IA-WMO-NEXT: sll a7, a7, a3
+; RV64IA-WMO-NEXT: sra a7, a7, a3
+; RV64IA-WMO-NEXT: bge a1, a7, .LBB51_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
+; RV64IA-WMO-NEXT: xor a6, a5, a1
+; RV64IA-WMO-NEXT: and a6, a6, a4
+; RV64IA-WMO-NEXT: xor a6, a5, a6
+; RV64IA-WMO-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-WMO-NEXT: bnez a6, .LBB51_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_min_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NEXT: li a4, 255
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: slli a1, a1, 56
+; RV64IA-TSO-NEXT: srai a1, a1, 56
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: xori a3, a3, 56
+; RV64IA-TSO-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-NEXT: and a7, a5, a4
+; RV64IA-TSO-NEXT: mv a6, a5
+; RV64IA-TSO-NEXT: sll a7, a7, a3
+; RV64IA-TSO-NEXT: sra a7, a7, a3
+; RV64IA-TSO-NEXT: bge a1, a7, .LBB51_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
+; RV64IA-TSO-NEXT: xor a6, a5, a1
+; RV64IA-TSO-NEXT: and a6, a6, a4
+; RV64IA-TSO-NEXT: xor a6, a5, a6
+; RV64IA-TSO-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NEXT: bnez a6, .LBB51_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b acquire
ret i8 %1
}
@@ -7128,131 +4807,63 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NOZACAS-NEXT: li a4, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-WMO-NOZACAS-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a6, a5
-; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB52_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-WMO-NOZACAS-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB52_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_min_i8_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NOZACAS-NEXT: li a4, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-TSO-NOZACAS-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a6, a5
-; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB52_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-TSO-NOZACAS-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB52_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i8_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-ZACAS-NEXT: li a4, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-WMO-ZACAS-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a6, a5
-; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB52_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-WMO-ZACAS-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB52_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_min_i8_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-ZACAS-NEXT: li a4, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-TSO-ZACAS-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a6, a5
-; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB52_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-TSO-ZACAS-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB52_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomin.b.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_min_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NEXT: li a4, 255
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: slli a1, a1, 56
+; RV64IA-WMO-NEXT: srai a1, a1, 56
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: xori a3, a3, 56
+; RV64IA-WMO-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a5, (a2)
+; RV64IA-WMO-NEXT: and a7, a5, a4
+; RV64IA-WMO-NEXT: mv a6, a5
+; RV64IA-WMO-NEXT: sll a7, a7, a3
+; RV64IA-WMO-NEXT: sra a7, a7, a3
+; RV64IA-WMO-NEXT: bge a1, a7, .LBB52_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
+; RV64IA-WMO-NEXT: xor a6, a5, a1
+; RV64IA-WMO-NEXT: and a6, a6, a4
+; RV64IA-WMO-NEXT: xor a6, a5, a6
+; RV64IA-WMO-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NEXT: bnez a6, .LBB52_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_min_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NEXT: li a4, 255
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: slli a1, a1, 56
+; RV64IA-TSO-NEXT: srai a1, a1, 56
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: xori a3, a3, 56
+; RV64IA-TSO-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-NEXT: and a7, a5, a4
+; RV64IA-TSO-NEXT: mv a6, a5
+; RV64IA-TSO-NEXT: sll a7, a7, a3
+; RV64IA-TSO-NEXT: sra a7, a7, a3
+; RV64IA-TSO-NEXT: bge a1, a7, .LBB52_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
+; RV64IA-TSO-NEXT: xor a6, a5, a1
+; RV64IA-TSO-NEXT: and a6, a6, a4
+; RV64IA-TSO-NEXT: xor a6, a5, a6
+; RV64IA-TSO-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NEXT: bnez a6, .LBB52_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b release
ret i8 %1
}
@@ -7400,131 +5011,63 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NOZACAS-NEXT: li a4, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-WMO-NOZACAS-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a6, a5
-; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB53_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-WMO-NOZACAS-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB53_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_min_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NEXT: li a4, 255
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: slli a1, a1, 56
+; RV64IA-WMO-NEXT: srai a1, a1, 56
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: xori a3, a3, 56
+; RV64IA-WMO-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a5, (a2)
+; RV64IA-WMO-NEXT: and a7, a5, a4
+; RV64IA-WMO-NEXT: mv a6, a5
+; RV64IA-WMO-NEXT: sll a7, a7, a3
+; RV64IA-WMO-NEXT: sra a7, a7, a3
+; RV64IA-WMO-NEXT: bge a1, a7, .LBB53_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
+; RV64IA-WMO-NEXT: xor a6, a5, a1
+; RV64IA-WMO-NEXT: and a6, a6, a4
+; RV64IA-WMO-NEXT: xor a6, a5, a6
+; RV64IA-WMO-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NEXT: bnez a6, .LBB53_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_min_i8_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NOZACAS-NEXT: li a4, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-TSO-NOZACAS-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a6, a5
-; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB53_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-TSO-NOZACAS-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB53_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i8_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-ZACAS-NEXT: li a4, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-WMO-ZACAS-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a6, a5
-; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB53_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-WMO-ZACAS-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB53_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_min_i8_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-ZACAS-NEXT: li a4, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-TSO-ZACAS-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a6, a5
-; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB53_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-TSO-ZACAS-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB53_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomin.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_min_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NEXT: li a4, 255
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: slli a1, a1, 56
+; RV64IA-TSO-NEXT: srai a1, a1, 56
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: xori a3, a3, 56
+; RV64IA-TSO-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-NEXT: and a7, a5, a4
+; RV64IA-TSO-NEXT: mv a6, a5
+; RV64IA-TSO-NEXT: sll a7, a7, a3
+; RV64IA-TSO-NEXT: sra a7, a7, a3
+; RV64IA-TSO-NEXT: bge a1, a7, .LBB53_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
+; RV64IA-TSO-NEXT: xor a6, a5, a1
+; RV64IA-TSO-NEXT: and a6, a6, a4
+; RV64IA-TSO-NEXT: xor a6, a5, a6
+; RV64IA-TSO-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NEXT: bnez a6, .LBB53_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -7643,73 +5186,34 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_min_i8_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-NOZACAS-NEXT: li a4, 255
-; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-NOZACAS-NEXT: slli a1, a1, 56
-; RV64IA-NOZACAS-NEXT: srai a1, a1, 56
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: xori a3, a3, 56
-; RV64IA-NOZACAS-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a5, (a2)
-; RV64IA-NOZACAS-NEXT: and a7, a5, a4
-; RV64IA-NOZACAS-NEXT: mv a6, a5
-; RV64IA-NOZACAS-NEXT: sll a7, a7, a3
-; RV64IA-NOZACAS-NEXT: sra a7, a7, a3
-; RV64IA-NOZACAS-NEXT: bge a1, a7, .LBB54_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a6, a5, a1
-; RV64IA-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-NOZACAS-NEXT: xor a6, a5, a6
-; RV64IA-NOZACAS-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a6, .LBB54_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_min_i8_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-ZACAS-NEXT: li a4, 255
-; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-ZACAS-NEXT: slli a1, a1, 56
-; RV64IA-ZACAS-NEXT: srai a1, a1, 56
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: xori a3, a3, 56
-; RV64IA-ZACAS-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a5, (a2)
-; RV64IA-ZACAS-NEXT: and a7, a5, a4
-; RV64IA-ZACAS-NEXT: mv a6, a5
-; RV64IA-ZACAS-NEXT: sll a7, a7, a3
-; RV64IA-ZACAS-NEXT: sra a7, a7, a3
-; RV64IA-ZACAS-NEXT: bge a1, a7, .LBB54_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a6, a5, a1
-; RV64IA-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-ZACAS-NEXT: xor a6, a5, a6
-; RV64IA-ZACAS-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-ZACAS-NEXT: bnez a6, .LBB54_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a5, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomin.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_min_i8_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: li a4, 255
+; RV64IA-NEXT: sllw a4, a4, a0
+; RV64IA-NEXT: slli a1, a1, 56
+; RV64IA-NEXT: srai a1, a1, 56
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: xori a3, a3, 56
+; RV64IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a5, (a2)
+; RV64IA-NEXT: and a7, a5, a4
+; RV64IA-NEXT: mv a6, a5
+; RV64IA-NEXT: sll a7, a7, a3
+; RV64IA-NEXT: sra a7, a7, a3
+; RV64IA-NEXT: bge a1, a7, .LBB54_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1
+; RV64IA-NEXT: xor a6, a5, a1
+; RV64IA-NEXT: and a6, a6, a4
+; RV64IA-NEXT: xor a6, a5, a6
+; RV64IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1
+; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-NEXT: bnez a6, .LBB54_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a5, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -7819,63 +5323,29 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i8_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a3, 255
-; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-NOZACAS-NEXT: mv a5, a4
-; RV64IA-NOZACAS-NEXT: bgeu a6, a1, .LBB55_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB55_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: .LBB55_3: # in Loop: Header=BB55_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB55_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_umax_i8_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a3, 255
-; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-ZACAS-NEXT: mv a5, a4
-; RV64IA-ZACAS-NEXT: bgeu a6, a1, .LBB55_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB55_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: .LBB55_3: # in Loop: Header=BB55_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB55_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomaxu.b a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_umax_i8_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a3, 255
+; RV64IA-NEXT: sllw a3, a3, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a4, (a2)
+; RV64IA-NEXT: and a6, a4, a3
+; RV64IA-NEXT: mv a5, a4
+; RV64IA-NEXT: bgeu a6, a1, .LBB55_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB55_1 Depth=1
+; RV64IA-NEXT: xor a5, a4, a1
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: .LBB55_3: # in Loop: Header=BB55_1 Depth=1
+; RV64IA-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB55_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a4, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -8009,111 +5479,53 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB56_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB56_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i8_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB56_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB56_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i8_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a4
-; RV64IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB56_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB56_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umax_i8_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a4
-; RV64IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB56_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB56_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomaxu.b.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umax_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NEXT: and a6, a4, a3
+; RV64IA-WMO-NEXT: mv a5, a4
+; RV64IA-WMO-NEXT: bgeu a6, a1, .LBB56_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a4, a1
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB56_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_umax_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: and a6, a4, a3
+; RV64IA-TSO-NEXT: mv a5, a4
+; RV64IA-TSO-NEXT: bgeu a6, a1, .LBB56_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a4, a1
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB56_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b acquire
ret i8 %1
}
@@ -8247,111 +5659,53 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB57_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB57_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i8_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB57_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB57_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i8_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a4
-; RV64IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB57_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB57_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umax_i8_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a4
-; RV64IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB57_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB57_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomaxu.b.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umax_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-NEXT: and a6, a4, a3
+; RV64IA-WMO-NEXT: mv a5, a4
+; RV64IA-WMO-NEXT: bgeu a6, a1, .LBB57_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a4, a1
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB57_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_umax_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: and a6, a4, a3
+; RV64IA-TSO-NEXT: mv a5, a4
+; RV64IA-TSO-NEXT: bgeu a6, a1, .LBB57_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a4, a1
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB57_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b release
ret i8 %1
}
@@ -8485,111 +5839,53 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB58_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB58_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i8_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB58_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB58_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i8_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a4
-; RV64IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB58_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB58_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umax_i8_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a4
-; RV64IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB58_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB58_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomaxu.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umax_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NEXT: and a6, a4, a3
+; RV64IA-WMO-NEXT: mv a5, a4
+; RV64IA-WMO-NEXT: bgeu a6, a1, .LBB58_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a4, a1
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB58_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_umax_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: and a6, a4, a3
+; RV64IA-TSO-NEXT: mv a5, a4
+; RV64IA-TSO-NEXT: bgeu a6, a1, .LBB58_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a4, a1
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB58_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -8699,63 +5995,29 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i8_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a3, 255
-; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-NOZACAS-NEXT: mv a5, a4
-; RV64IA-NOZACAS-NEXT: bgeu a6, a1, .LBB59_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB59_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: .LBB59_3: # in Loop: Header=BB59_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB59_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_umax_i8_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a3, 255
-; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-ZACAS-NEXT: mv a5, a4
-; RV64IA-ZACAS-NEXT: bgeu a6, a1, .LBB59_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB59_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: .LBB59_3: # in Loop: Header=BB59_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB59_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomaxu.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_umax_i8_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a3, 255
+; RV64IA-NEXT: sllw a3, a3, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-NEXT: and a6, a4, a3
+; RV64IA-NEXT: mv a5, a4
+; RV64IA-NEXT: bgeu a6, a1, .LBB59_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB59_1 Depth=1
+; RV64IA-NEXT: xor a5, a4, a1
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: .LBB59_3: # in Loop: Header=BB59_1 Depth=1
+; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB59_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a4, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -8865,63 +6127,29 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i8_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a3, 255
-; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-NOZACAS-NEXT: mv a5, a4
-; RV64IA-NOZACAS-NEXT: bgeu a1, a6, .LBB60_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB60_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: .LBB60_3: # in Loop: Header=BB60_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB60_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_umin_i8_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a3, 255
-; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-ZACAS-NEXT: mv a5, a4
-; RV64IA-ZACAS-NEXT: bgeu a1, a6, .LBB60_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB60_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: .LBB60_3: # in Loop: Header=BB60_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB60_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amominu.b a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_umin_i8_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a3, 255
+; RV64IA-NEXT: sllw a3, a3, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a4, (a2)
+; RV64IA-NEXT: and a6, a4, a3
+; RV64IA-NEXT: mv a5, a4
+; RV64IA-NEXT: bgeu a1, a6, .LBB60_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB60_1 Depth=1
+; RV64IA-NEXT: xor a5, a4, a1
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: .LBB60_3: # in Loop: Header=BB60_1 Depth=1
+; RV64IA-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB60_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a4, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -9055,111 +6283,53 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB61_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB61_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i8_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB61_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB61_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i8_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a4
-; RV64IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB61_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB61_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umin_i8_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a4
-; RV64IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB61_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB61_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amominu.b.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umin_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NEXT: and a6, a4, a3
+; RV64IA-WMO-NEXT: mv a5, a4
+; RV64IA-WMO-NEXT: bgeu a1, a6, .LBB61_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a4, a1
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB61_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_umin_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: and a6, a4, a3
+; RV64IA-TSO-NEXT: mv a5, a4
+; RV64IA-TSO-NEXT: bgeu a1, a6, .LBB61_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a4, a1
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB61_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b acquire
ret i8 %1
}
@@ -9293,111 +6463,53 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB62_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB62_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i8_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB62_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB62_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i8_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a4
-; RV64IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB62_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB62_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umin_i8_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a4
-; RV64IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB62_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB62_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amominu.b.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umin_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-NEXT: and a6, a4, a3
+; RV64IA-WMO-NEXT: mv a5, a4
+; RV64IA-WMO-NEXT: bgeu a1, a6, .LBB62_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a4, a1
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB62_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_umin_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: and a6, a4, a3
+; RV64IA-TSO-NEXT: mv a5, a4
+; RV64IA-TSO-NEXT: bgeu a1, a6, .LBB62_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a4, a1
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB62_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b release
ret i8 %1
}
@@ -9531,111 +6643,53 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB63_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NOZACAS-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB63_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i8_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB63_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NOZACAS-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB63_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i8_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: li a3, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a4
-; RV64IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB63_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-WMO-ZACAS-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB63_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umin_i8_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: li a3, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a4
-; RV64IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB63_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-TSO-ZACAS-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB63_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amominu.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umin_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a3, 255
+; RV64IA-WMO-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NEXT: and a6, a4, a3
+; RV64IA-WMO-NEXT: mv a5, a4
+; RV64IA-WMO-NEXT: bgeu a1, a6, .LBB63_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a4, a1
+; RV64IA-WMO-NEXT: and a5, a5, a3
+; RV64IA-WMO-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB63_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_umin_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a3, 255
+; RV64IA-TSO-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NEXT: and a6, a4, a3
+; RV64IA-TSO-NEXT: mv a5, a4
+; RV64IA-TSO-NEXT: bgeu a1, a6, .LBB63_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a4, a1
+; RV64IA-TSO-NEXT: and a5, a5, a3
+; RV64IA-TSO-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB63_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -9745,63 +6799,29 @@ define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i8_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: li a3, 255
-; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-NOZACAS-NEXT: and a6, a4, a3
-; RV64IA-NOZACAS-NEXT: mv a5, a4
-; RV64IA-NOZACAS-NEXT: bgeu a1, a6, .LBB64_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB64_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a1
-; RV64IA-NOZACAS-NEXT: and a5, a5, a3
-; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
-; RV64IA-NOZACAS-NEXT: .LBB64_3: # in Loop: Header=BB64_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB64_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_umin_i8_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: li a3, 255
-; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
-; RV64IA-ZACAS-NEXT: andi a1, a1, 255
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-ZACAS-NEXT: and a6, a4, a3
-; RV64IA-ZACAS-NEXT: mv a5, a4
-; RV64IA-ZACAS-NEXT: bgeu a1, a6, .LBB64_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB64_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a5, a4, a1
-; RV64IA-ZACAS-NEXT: and a5, a5, a3
-; RV64IA-ZACAS-NEXT: xor a5, a4, a5
-; RV64IA-ZACAS-NEXT: .LBB64_3: # in Loop: Header=BB64_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB64_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amominu.b.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_umin_i8_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: li a3, 255
+; RV64IA-NEXT: sllw a3, a3, a0
+; RV64IA-NEXT: andi a1, a1, 255
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-NEXT: and a6, a4, a3
+; RV64IA-NEXT: mv a5, a4
+; RV64IA-NEXT: bgeu a1, a6, .LBB64_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB64_1 Depth=1
+; RV64IA-NEXT: xor a5, a4, a1
+; RV64IA-NEXT: and a5, a5, a3
+; RV64IA-NEXT: xor a5, a4, a5
+; RV64IA-NEXT: .LBB64_3: # in Loop: Header=BB64_1 Depth=1
+; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB64_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a4, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -9848,57 +6868,26 @@ define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i16_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-NOZACAS-NEXT: mv a5, a1
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB65_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_xchg_i16_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a3, 16
-; RV64IA-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-ZACAS-NEXT: mv a5, a1
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB65_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_xchg_i16_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addi a3, a3, -1
+; RV64IA-NEXT: sllw a4, a3, a0
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a3, (a2)
+; RV64IA-NEXT: mv a5, a1
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB65_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -9966,99 +6955,47 @@ define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB66_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i16_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB66_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i16_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB66_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i16_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB66_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: mv a5, a1
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB66_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: mv a5, a1
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB66_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 %b acquire
ret i16 %1
}
@@ -10126,99 +7063,47 @@ define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB67_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i16_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB67_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i16_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB67_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i16_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB67_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NEXT: mv a5, a1
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB67_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: mv a5, a1
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB67_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 %b release
ret i16 %1
}
@@ -10286,99 +7171,47 @@ define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB68_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i16_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB68_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i16_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB68_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i16_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB68_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: mv a5, a1
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB68_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: mv a5, a1
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB68_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -10425,57 +7258,26 @@ define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i16_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NOZACAS-NEXT: mv a5, a1
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB69_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_xchg_i16_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a3, 16
-; RV64IA-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-ZACAS-NEXT: mv a5, a1
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB69_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_xchg_i16_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addi a3, a3, -1
+; RV64IA-NEXT: sllw a4, a3, a0
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NEXT: mv a5, a1
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB69_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -10518,39 +7320,17 @@ define i16 @atomicrmw_xchg_0_i16_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_0_i16_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a2, 16
-; RV64IA-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-NOZACAS-NEXT: not a2, a2
-; RV64IA-NOZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_xchg_0_i16_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a2, 16
-; RV64IA-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-ZACAS-NEXT: not a2, a2
-; RV64IA-ZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h a0, zero, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_xchg_0_i16_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a1, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a2, 16
+; RV64IA-NEXT: addi a2, a2, -1
+; RV64IA-NEXT: sllw a2, a2, a0
+; RV64IA-NEXT: not a2, a2
+; RV64IA-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-NEXT: srlw a0, a1, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 0 monotonic
ret i16 %1
}
@@ -10602,63 +7382,29 @@ define i16 @atomicrmw_xchg_0_i16_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aq a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: not a2, a2
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.aq a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i16_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: not a2, a2
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aq a0, zero, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aq a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 0 acquire
ret i16 %1
}
@@ -10710,63 +7456,29 @@ define i16 @atomicrmw_xchg_0_i16_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.rl a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.rl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: not a2, a2
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.rl a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i16_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: not a2, a2
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h.rl a0, zero, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 0 release
ret i16 %1
}
@@ -10818,63 +7530,29 @@ define i16 @atomicrmw_xchg_0_i16_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: not a2, a2
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: not a2, a2
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, zero, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 0 acq_rel
ret i16 %1
}
@@ -10926,63 +7604,29 @@ define i16 @atomicrmw_xchg_0_i16_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: not a2, a2
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: not a2, a2
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, zero, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i16_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i16_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 0 seq_cst
ret i16 %1
}
@@ -11023,39 +7667,16 @@ define i16 @atomicrmw_xchg_minus_1_i16_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a2, 16
-; RV64IA-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-NOZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a2, 16
-; RV64IA-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-ZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: li a1, -1
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: li a1, -1
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_xchg_minus_1_i16_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a1, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a2, 16
+; RV64IA-NEXT: addi a2, a2, -1
+; RV64IA-NEXT: sllw a2, a2, a0
+; RV64IA-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-NEXT: srlw a0, a1, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 -1 monotonic
ret i16 %1
}
@@ -11107,61 +7728,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aq a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.aq a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.aq a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: li a1, -1
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: li a1, -1
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 -1 acquire
ret i16 %1
}
@@ -11213,61 +7800,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.rl a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.rl a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.rl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: li a1, -1
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: li a1, -1
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 -1 release
ret i16 %1
}
@@ -11319,61 +7872,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: li a1, -1
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: li a1, -1
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 -1 acq_rel
ret i16 %1
}
@@ -11425,61 +7944,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a2, 16
+; RV64IA-WMO-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: li a1, -1
-; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: li a1, -1
-; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a2, 16
+; RV64IA-TSO-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 -1 seq_cst
ret i16 %1
}
@@ -11526,57 +8011,26 @@ define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_add_i16_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-NOZACAS-NEXT: add a5, a3, a1
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB80_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_add_i16_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a3, 16
-; RV64IA-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-ZACAS-NEXT: add a5, a3, a1
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB80_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_add_i16_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addi a3, a3, -1
+; RV64IA-NEXT: sllw a4, a3, a0
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a3, (a2)
+; RV64IA-NEXT: add a5, a3, a1
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB80_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw add ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -11644,99 +8098,47 @@ define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: add a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB81_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_add_i16_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: add a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB81_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i16_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: add a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB81_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_add_i16_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: add a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB81_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_add_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: add a5, a3, a1
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB81_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_add_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: add a5, a3, a1
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB81_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw add ptr %a, i16 %b acquire
ret i16 %1
}
@@ -11804,99 +8206,47 @@ define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: add a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB82_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_add_i16_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: add a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB82_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i16_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: add a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB82_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_add_i16_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: add a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB82_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoadd.h.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_add_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NEXT: add a5, a3, a1
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB82_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_add_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: add a5, a3, a1
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB82_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw add ptr %a, i16 %b release
ret i16 %1
}
@@ -11964,99 +8314,47 @@ define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: add a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB83_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_add_i16_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: add a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB83_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i16_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: add a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB83_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_add_i16_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: add a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB83_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_add_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: add a5, a3, a1
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB83_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_add_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: add a5, a3, a1
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB83_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw add ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -12103,57 +8401,26 @@ define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_add_i16_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NOZACAS-NEXT: add a5, a3, a1
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB84_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_add_i16_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a3, 16
-; RV64IA-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-ZACAS-NEXT: add a5, a3, a1
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB84_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_add_i16_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addi a3, a3, -1
+; RV64IA-NEXT: sllw a4, a3, a0
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NEXT: add a5, a3, a1
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB84_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw add ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -12200,59 +8467,26 @@ define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i16_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-NOZACAS-NEXT: sub a5, a3, a1
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB85_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_sub_i16_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a3, 16
-; RV64IA-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-ZACAS-NEXT: sub a5, a3, a1
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB85_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
-; RV64IA-WMO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
-; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_sub_i16_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addi a3, a3, -1
+; RV64IA-NEXT: sllw a4, a3, a0
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a3, (a2)
+; RV64IA-NEXT: sub a5, a3, a1
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB85_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw sub ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -12320,101 +8554,47 @@ define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: sub a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB86_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i16_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: sub a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB86_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i16_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: sub a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB86_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_sub_i16_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: sub a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB86_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_sub_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: sub a5, a3, a1
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB86_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
-; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
-; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_sub_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: sub a5, a3, a1
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB86_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw sub ptr %a, i16 %b acquire
ret i16 %1
}
@@ -12482,101 +8662,47 @@ define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: sub a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB87_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i16_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: sub a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB87_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i16_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: sub a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB87_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_sub_i16_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: sub a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB87_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_sub_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NEXT: sub a5, a3, a1
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB87_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
-; RV64IA-WMO-ZABHA-NEXT: amoadd.h.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
-; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_sub_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: sub a5, a3, a1
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB87_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw sub ptr %a, i16 %b release
ret i16 %1
}
@@ -12644,101 +8770,47 @@ define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: sub a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB88_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i16_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: sub a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB88_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i16_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: sub a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB88_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_sub_i16_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: sub a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB88_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_sub_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: sub a5, a3, a1
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB88_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
-; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
-; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_sub_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: sub a5, a3, a1
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB88_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw sub ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -12785,59 +8857,26 @@ define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i16_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NOZACAS-NEXT: sub a5, a3, a1
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB89_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_sub_i16_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a3, 16
-; RV64IA-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-ZACAS-NEXT: sub a5, a3, a1
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB89_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
-; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
-; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_sub_i16_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addi a3, a3, -1
+; RV64IA-NEXT: sllw a4, a3, a0
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NEXT: sub a5, a3, a1
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB89_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw sub ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -12878,45 +8917,20 @@ define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_and_i16_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-NOZACAS-NEXT: not a4, a4
-; RV64IA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: or a1, a4, a1
-; RV64IA-NOZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_and_i16_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a3, 16
-; RV64IA-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-ZACAS-NEXT: not a4, a4
-; RV64IA-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: or a1, a4, a1
-; RV64IA-ZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoand.h a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_and_i16_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addi a3, a3, -1
+; RV64IA-NEXT: sllw a4, a3, a0
+; RV64IA-NEXT: not a4, a4
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: or a1, a4, a1
+; RV64IA-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-NEXT: srlw a0, a1, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -12972,75 +8986,35 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a4, a4
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aq a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i16_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a4, a4
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: not a4, a4
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.aq a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i16_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: not a4, a4
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoand.h.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: not a4, a4
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a4, a1
+; RV64IA-WMO-NEXT: amoand.w.aq a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_and_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: not a4, a4
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a4, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b acquire
ret i16 %1
}
@@ -13096,75 +9070,35 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a4, a4
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.rl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i16_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a4, a4
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: not a4, a4
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.rl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i16_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: not a4, a4
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoand.h.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: not a4, a4
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a4, a1
+; RV64IA-WMO-NEXT: amoand.w.rl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_and_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: not a4, a4
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a4, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b release
ret i16 %1
}
@@ -13220,75 +9154,35 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a4, a4
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i16_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a4, a4
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: not a4, a4
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i16_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: not a4, a4
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoand.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: not a4, a4
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a4, a1
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_and_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: not a4, a4
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a4, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -13332,87 +9226,47 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32IA-TSO-NEXT: or a1, a4, a1
; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2)
; RV32IA-TSO-NEXT: srl a0, a1, a0
-; RV32IA-TSO-NEXT: ret
-;
-; RV64I-LABEL: atomicrmw_and_i16_seq_cst:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -16
-; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: li a2, 5
-; RV64I-NEXT: call __atomic_fetch_and_2
-; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 16
-; RV64I-NEXT: ret
-;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_seq_cst:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: not a4, a4
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: or a1, a4, a1
-; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i16_seq_cst:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: not a4, a4
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: or a1, a4, a1
-; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_seq_cst:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: not a4, a4
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: or a1, a4, a1
-; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
+; RV32IA-TSO-NEXT: ret
;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i16_seq_cst:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: not a4, a4
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: or a1, a4, a1
-; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64I-LABEL: atomicrmw_and_i16_seq_cst:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: li a2, 5
+; RV64I-NEXT: call __atomic_fetch_and_2
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoand.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_and_i16_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: not a4, a4
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: or a1, a4, a1
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_and_i16_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: not a4, a4
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: or a1, a4, a1
+; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -13460,123 +9314,27 @@ define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i16_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-NOZACAS-NEXT: not a5, a5
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB95_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_nand_i16_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a3, 16
-; RV64IA-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-ZACAS-NEXT: and a5, a3, a1
-; RV64IA-ZACAS-NEXT: not a5, a5
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB95_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_monotonic:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB95_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_monotonic:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB95_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_monotonic:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB95_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB95_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_monotonic:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB95_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB95_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
+; RV64IA-LABEL: atomicrmw_nand_i16_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addi a3, a3, -1
+; RV64IA-NEXT: sllw a4, a3, a0
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a3, (a2)
+; RV64IA-NEXT: and a5, a3, a1
+; RV64IA-NEXT: not a5, a5
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB95_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw nand ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -13646,167 +9404,49 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB96_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i16_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB96_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i16_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB96_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_nand_i16_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB96_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_nand_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: and a5, a3, a1
+; RV64IA-WMO-NEXT: not a5, a5
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB96_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_acquire:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB96_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_acquire:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB96_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_acquire:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB96_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.h.aq a0, a3, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB96_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_acquire:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB96_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB96_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_nand_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a5, a3, a1
+; RV64IA-TSO-NEXT: not a5, a5
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB96_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw nand ptr %a, i16 %b acquire
ret i16 %1
}
@@ -13876,167 +9516,49 @@ define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB97_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i16_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB97_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i16_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB97_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_nand_i16_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB97_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_nand_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NEXT: and a5, a3, a1
+; RV64IA-WMO-NEXT: not a5, a5
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB97_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_release:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB97_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_release:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB97_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_release:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB97_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.h.rl a0, a3, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB97_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_release:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB97_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB97_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_nand_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a5, a3, a1
+; RV64IA-TSO-NEXT: not a5, a5
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB97_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw nand ptr %a, i16 %b release
ret i16 %1
}
@@ -14106,167 +9628,49 @@ define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB98_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB98_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB98_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB98_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_nand_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: and a5, a3, a1
+; RV64IA-WMO-NEXT: not a5, a5
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB98_1
+; RV64IA-WMO-NEXT: # %bb.2:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB98_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB98_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB98_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.h.aqrl a0, a3, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB98_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB98_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB98_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_nand_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a5, a3, a1
+; RV64IA-TSO-NEXT: not a5, a5
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB98_1
+; RV64IA-TSO-NEXT: # %bb.2:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw nand ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -14314,123 +9718,27 @@ define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i16_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-NOZACAS-NEXT: not a5, a5
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB99_1
-; RV64IA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_nand_i16_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a3, 16
-; RV64IA-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-ZACAS-NEXT: and a5, a3, a1
-; RV64IA-ZACAS-NEXT: not a5, a5
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB99_1
-; RV64IA-ZACAS-NEXT: # %bb.2:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_seq_cst:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB99_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_seq_cst:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB99_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_seq_cst:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB99_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.h.aqrl a0, a3, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB99_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_seq_cst:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB99_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB99_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
+; RV64IA-LABEL: atomicrmw_nand_i16_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addi a3, a3, -1
+; RV64IA-NEXT: sllw a4, a3, a0
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NEXT: and a5, a3, a1
+; RV64IA-NEXT: not a5, a5
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB99_1
+; RV64IA-NEXT: # %bb.2:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw nand ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -14467,37 +9775,16 @@ define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_or_i16_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_or_i16_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoor.h a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_or_i16_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slli a1, a1, 48
+; RV64IA-NEXT: srli a1, a1, 48
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-NEXT: srlw a0, a1, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -14545,59 +9832,27 @@ define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aq a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i16_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.aq a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i16_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoor.h.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.aq a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_or_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b acquire
ret i16 %1
}
@@ -14645,59 +9900,27 @@ define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.rl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i16_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.rl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i16_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoor.h.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.rl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_or_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b release
ret i16 %1
}
@@ -14745,59 +9968,27 @@ define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i16_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i16_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoor.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_or_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -14845,59 +10036,27 @@ define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_seq_cst:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i16_seq_cst:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_seq_cst:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i16_seq_cst:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoor.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_or_i16_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_or_i16_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -14934,37 +10093,16 @@ define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_xor_i16_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_xor_i16_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoxor.h a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_xor_i16_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slli a1, a1, 48
+; RV64IA-NEXT: srli a1, a1, 48
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-NEXT: srlw a0, a1, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -15012,59 +10150,27 @@ define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.aq a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i16_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoxor.w.aq a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i16_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoxor.h.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.aq a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xor_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b acquire
ret i16 %1
}
@@ -15112,59 +10218,27 @@ define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.rl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i16_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoxor.w.rl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i16_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoxor.h.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.rl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xor_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b release
ret i16 %1
}
@@ -15212,59 +10286,27 @@ define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i16_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i16_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoxor.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -15312,59 +10354,27 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_seq_cst:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i16_seq_cst:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_seq_cst:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i16_seq_cst:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amoxor.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -15485,77 +10495,36 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_max_i16_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-NOZACAS-NEXT: lui a4, 16
-; RV64IA-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: li a5, 48
-; RV64IA-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-NOZACAS-NEXT: .LBB110_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-NOZACAS-NEXT: mv a6, a3
-; RV64IA-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-NOZACAS-NEXT: bge a7, a1, .LBB110_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB110_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-NOZACAS-NEXT: .LBB110_3: # in Loop: Header=BB110_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a6, .LBB110_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_max_i16_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-ZACAS-NEXT: lui a4, 16
-; RV64IA-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: li a5, 48
-; RV64IA-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-ZACAS-NEXT: .LBB110_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-ZACAS-NEXT: mv a6, a3
-; RV64IA-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-ZACAS-NEXT: bge a7, a1, .LBB110_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB110_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-ZACAS-NEXT: .LBB110_3: # in Loop: Header=BB110_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-ZACAS-NEXT: bnez a6, .LBB110_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomax.h a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_max_i16_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addi a4, a4, -1
+; RV64IA-NEXT: sllw a4, a4, a0
+; RV64IA-NEXT: slli a1, a1, 48
+; RV64IA-NEXT: srai a1, a1, 48
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: li a5, 48
+; RV64IA-NEXT: sub a5, a5, a3
+; RV64IA-NEXT: .LBB110_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a3, (a2)
+; RV64IA-NEXT: and a7, a3, a4
+; RV64IA-NEXT: mv a6, a3
+; RV64IA-NEXT: sll a7, a7, a5
+; RV64IA-NEXT: sra a7, a7, a5
+; RV64IA-NEXT: bge a7, a1, .LBB110_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB110_1 Depth=1
+; RV64IA-NEXT: xor a6, a3, a1
+; RV64IA-NEXT: and a6, a6, a4
+; RV64IA-NEXT: xor a6, a3, a6
+; RV64IA-NEXT: .LBB110_3: # in Loop: Header=BB110_1 Depth=1
+; RV64IA-NEXT: sc.w a6, a6, (a2)
+; RV64IA-NEXT: bnez a6, .LBB110_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -15703,143 +10672,71 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
-; RV64I-NEXT: ret
-;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NOZACAS-NEXT: lui a4, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: li a5, 48
-; RV64IA-WMO-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a6, a3
-; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB111_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-WMO-NOZACAS-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB111_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_max_i16_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NOZACAS-NEXT: lui a4, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: li a5, 48
-; RV64IA-TSO-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a6, a3
-; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB111_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-TSO-NOZACAS-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB111_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i16_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: li a5, 48
-; RV64IA-WMO-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a6, a3
-; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB111_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-WMO-ZACAS-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB111_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_max_i16_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: li a5, 48
-; RV64IA-TSO-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a6, a3
-; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB111_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-TSO-ZACAS-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB111_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
+; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ret
;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomax.h.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_max_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NEXT: lui a4, 16
+; RV64IA-WMO-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srai a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: li a5, 48
+; RV64IA-WMO-NEXT: sub a5, a5, a3
+; RV64IA-WMO-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: and a7, a3, a4
+; RV64IA-WMO-NEXT: mv a6, a3
+; RV64IA-WMO-NEXT: sll a7, a7, a5
+; RV64IA-WMO-NEXT: sra a7, a7, a5
+; RV64IA-WMO-NEXT: bge a7, a1, .LBB111_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1
+; RV64IA-WMO-NEXT: xor a6, a3, a1
+; RV64IA-WMO-NEXT: and a6, a6, a4
+; RV64IA-WMO-NEXT: xor a6, a3, a6
+; RV64IA-WMO-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-WMO-NEXT: bnez a6, .LBB111_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_max_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NEXT: lui a4, 16
+; RV64IA-TSO-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srai a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: li a5, 48
+; RV64IA-TSO-NEXT: sub a5, a5, a3
+; RV64IA-TSO-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a7, a3, a4
+; RV64IA-TSO-NEXT: mv a6, a3
+; RV64IA-TSO-NEXT: sll a7, a7, a5
+; RV64IA-TSO-NEXT: sra a7, a7, a5
+; RV64IA-TSO-NEXT: bge a7, a1, .LBB111_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1
+; RV64IA-TSO-NEXT: xor a6, a3, a1
+; RV64IA-TSO-NEXT: and a6, a6, a4
+; RV64IA-TSO-NEXT: xor a6, a3, a6
+; RV64IA-TSO-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NEXT: bnez a6, .LBB111_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b acquire
ret i16 %1
}
@@ -15991,139 +10888,67 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NOZACAS-NEXT: lui a4, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: li a5, 48
-; RV64IA-WMO-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a6, a3
-; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB112_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-WMO-NOZACAS-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB112_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_max_i16_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NOZACAS-NEXT: lui a4, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: li a5, 48
-; RV64IA-TSO-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a6, a3
-; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB112_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-TSO-NOZACAS-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB112_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i16_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: li a5, 48
-; RV64IA-WMO-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a6, a3
-; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB112_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-WMO-ZACAS-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB112_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_max_i16_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: li a5, 48
-; RV64IA-TSO-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a6, a3
-; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB112_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-TSO-ZACAS-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB112_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomax.h.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_max_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NEXT: lui a4, 16
+; RV64IA-WMO-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srai a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: li a5, 48
+; RV64IA-WMO-NEXT: sub a5, a5, a3
+; RV64IA-WMO-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NEXT: and a7, a3, a4
+; RV64IA-WMO-NEXT: mv a6, a3
+; RV64IA-WMO-NEXT: sll a7, a7, a5
+; RV64IA-WMO-NEXT: sra a7, a7, a5
+; RV64IA-WMO-NEXT: bge a7, a1, .LBB112_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1
+; RV64IA-WMO-NEXT: xor a6, a3, a1
+; RV64IA-WMO-NEXT: and a6, a6, a4
+; RV64IA-WMO-NEXT: xor a6, a3, a6
+; RV64IA-WMO-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NEXT: bnez a6, .LBB112_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_max_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NEXT: lui a4, 16
+; RV64IA-TSO-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srai a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: li a5, 48
+; RV64IA-TSO-NEXT: sub a5, a5, a3
+; RV64IA-TSO-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a7, a3, a4
+; RV64IA-TSO-NEXT: mv a6, a3
+; RV64IA-TSO-NEXT: sll a7, a7, a5
+; RV64IA-TSO-NEXT: sra a7, a7, a5
+; RV64IA-TSO-NEXT: bge a7, a1, .LBB112_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1
+; RV64IA-TSO-NEXT: xor a6, a3, a1
+; RV64IA-TSO-NEXT: and a6, a6, a4
+; RV64IA-TSO-NEXT: xor a6, a3, a6
+; RV64IA-TSO-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NEXT: bnez a6, .LBB112_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b release
ret i16 %1
}
@@ -16275,139 +11100,67 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NOZACAS-NEXT: lui a4, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: li a5, 48
-; RV64IA-WMO-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a6, a3
-; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB113_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-WMO-NOZACAS-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB113_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_max_i16_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NOZACAS-NEXT: lui a4, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: li a5, 48
-; RV64IA-TSO-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a6, a3
-; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB113_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-TSO-NOZACAS-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB113_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i16_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: li a5, 48
-; RV64IA-WMO-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a6, a3
-; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB113_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-WMO-ZACAS-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB113_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_max_i16_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: li a5, 48
-; RV64IA-TSO-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a6, a3
-; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB113_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-TSO-ZACAS-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB113_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomax.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_max_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NEXT: lui a4, 16
+; RV64IA-WMO-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srai a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: li a5, 48
+; RV64IA-WMO-NEXT: sub a5, a5, a3
+; RV64IA-WMO-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: and a7, a3, a4
+; RV64IA-WMO-NEXT: mv a6, a3
+; RV64IA-WMO-NEXT: sll a7, a7, a5
+; RV64IA-WMO-NEXT: sra a7, a7, a5
+; RV64IA-WMO-NEXT: bge a7, a1, .LBB113_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1
+; RV64IA-WMO-NEXT: xor a6, a3, a1
+; RV64IA-WMO-NEXT: and a6, a6, a4
+; RV64IA-WMO-NEXT: xor a6, a3, a6
+; RV64IA-WMO-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NEXT: bnez a6, .LBB113_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_max_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NEXT: lui a4, 16
+; RV64IA-TSO-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srai a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: li a5, 48
+; RV64IA-TSO-NEXT: sub a5, a5, a3
+; RV64IA-TSO-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a7, a3, a4
+; RV64IA-TSO-NEXT: mv a6, a3
+; RV64IA-TSO-NEXT: sll a7, a7, a5
+; RV64IA-TSO-NEXT: sra a7, a7, a5
+; RV64IA-TSO-NEXT: bge a7, a1, .LBB113_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1
+; RV64IA-TSO-NEXT: xor a6, a3, a1
+; RV64IA-TSO-NEXT: and a6, a6, a4
+; RV64IA-TSO-NEXT: xor a6, a3, a6
+; RV64IA-TSO-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NEXT: bnez a6, .LBB113_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -16528,77 +11281,36 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_max_i16_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-NOZACAS-NEXT: lui a4, 16
-; RV64IA-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: li a5, 48
-; RV64IA-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-NOZACAS-NEXT: .LBB114_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-NOZACAS-NEXT: mv a6, a3
-; RV64IA-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-NOZACAS-NEXT: bge a7, a1, .LBB114_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB114_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-NOZACAS-NEXT: .LBB114_3: # in Loop: Header=BB114_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a6, .LBB114_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_max_i16_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-ZACAS-NEXT: lui a4, 16
-; RV64IA-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: li a5, 48
-; RV64IA-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-ZACAS-NEXT: .LBB114_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-ZACAS-NEXT: mv a6, a3
-; RV64IA-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-ZACAS-NEXT: bge a7, a1, .LBB114_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB114_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-ZACAS-NEXT: .LBB114_3: # in Loop: Header=BB114_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-ZACAS-NEXT: bnez a6, .LBB114_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomax.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_max_i16_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addi a4, a4, -1
+; RV64IA-NEXT: sllw a4, a4, a0
+; RV64IA-NEXT: slli a1, a1, 48
+; RV64IA-NEXT: srai a1, a1, 48
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: li a5, 48
+; RV64IA-NEXT: sub a5, a5, a3
+; RV64IA-NEXT: .LBB114_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NEXT: and a7, a3, a4
+; RV64IA-NEXT: mv a6, a3
+; RV64IA-NEXT: sll a7, a7, a5
+; RV64IA-NEXT: sra a7, a7, a5
+; RV64IA-NEXT: bge a7, a1, .LBB114_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB114_1 Depth=1
+; RV64IA-NEXT: xor a6, a3, a1
+; RV64IA-NEXT: and a6, a6, a4
+; RV64IA-NEXT: xor a6, a3, a6
+; RV64IA-NEXT: .LBB114_3: # in Loop: Header=BB114_1 Depth=1
+; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-NEXT: bnez a6, .LBB114_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -16719,77 +11431,36 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_min_i16_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-NOZACAS-NEXT: lui a4, 16
-; RV64IA-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: li a5, 48
-; RV64IA-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-NOZACAS-NEXT: .LBB115_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-NOZACAS-NEXT: mv a6, a3
-; RV64IA-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-NOZACAS-NEXT: bge a1, a7, .LBB115_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB115_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-NOZACAS-NEXT: .LBB115_3: # in Loop: Header=BB115_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a6, .LBB115_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_min_i16_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-ZACAS-NEXT: lui a4, 16
-; RV64IA-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: li a5, 48
-; RV64IA-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-ZACAS-NEXT: .LBB115_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-ZACAS-NEXT: mv a6, a3
-; RV64IA-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-ZACAS-NEXT: bge a1, a7, .LBB115_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB115_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-ZACAS-NEXT: .LBB115_3: # in Loop: Header=BB115_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-ZACAS-NEXT: bnez a6, .LBB115_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomin.h a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_min_i16_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addi a4, a4, -1
+; RV64IA-NEXT: sllw a4, a4, a0
+; RV64IA-NEXT: slli a1, a1, 48
+; RV64IA-NEXT: srai a1, a1, 48
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: li a5, 48
+; RV64IA-NEXT: sub a5, a5, a3
+; RV64IA-NEXT: .LBB115_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a3, (a2)
+; RV64IA-NEXT: and a7, a3, a4
+; RV64IA-NEXT: mv a6, a3
+; RV64IA-NEXT: sll a7, a7, a5
+; RV64IA-NEXT: sra a7, a7, a5
+; RV64IA-NEXT: bge a1, a7, .LBB115_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB115_1 Depth=1
+; RV64IA-NEXT: xor a6, a3, a1
+; RV64IA-NEXT: and a6, a6, a4
+; RV64IA-NEXT: xor a6, a3, a6
+; RV64IA-NEXT: .LBB115_3: # in Loop: Header=BB115_1 Depth=1
+; RV64IA-NEXT: sc.w a6, a6, (a2)
+; RV64IA-NEXT: bnez a6, .LBB115_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -16941,139 +11612,67 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NOZACAS-NEXT: lui a4, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: li a5, 48
-; RV64IA-WMO-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a6, a3
-; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB116_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-WMO-NOZACAS-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB116_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_min_i16_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NOZACAS-NEXT: lui a4, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: li a5, 48
-; RV64IA-TSO-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a6, a3
-; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB116_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-TSO-NOZACAS-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB116_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i16_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: li a5, 48
-; RV64IA-WMO-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a6, a3
-; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB116_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-WMO-ZACAS-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB116_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_min_i16_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: li a5, 48
-; RV64IA-TSO-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a6, a3
-; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB116_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-TSO-ZACAS-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB116_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomin.h.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_min_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NEXT: lui a4, 16
+; RV64IA-WMO-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srai a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: li a5, 48
+; RV64IA-WMO-NEXT: sub a5, a5, a3
+; RV64IA-WMO-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: and a7, a3, a4
+; RV64IA-WMO-NEXT: mv a6, a3
+; RV64IA-WMO-NEXT: sll a7, a7, a5
+; RV64IA-WMO-NEXT: sra a7, a7, a5
+; RV64IA-WMO-NEXT: bge a1, a7, .LBB116_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1
+; RV64IA-WMO-NEXT: xor a6, a3, a1
+; RV64IA-WMO-NEXT: and a6, a6, a4
+; RV64IA-WMO-NEXT: xor a6, a3, a6
+; RV64IA-WMO-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-WMO-NEXT: bnez a6, .LBB116_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_min_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NEXT: lui a4, 16
+; RV64IA-TSO-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srai a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: li a5, 48
+; RV64IA-TSO-NEXT: sub a5, a5, a3
+; RV64IA-TSO-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a7, a3, a4
+; RV64IA-TSO-NEXT: mv a6, a3
+; RV64IA-TSO-NEXT: sll a7, a7, a5
+; RV64IA-TSO-NEXT: sra a7, a7, a5
+; RV64IA-TSO-NEXT: bge a1, a7, .LBB116_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1
+; RV64IA-TSO-NEXT: xor a6, a3, a1
+; RV64IA-TSO-NEXT: and a6, a6, a4
+; RV64IA-TSO-NEXT: xor a6, a3, a6
+; RV64IA-TSO-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NEXT: bnez a6, .LBB116_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b acquire
ret i16 %1
}
@@ -17225,139 +11824,67 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NOZACAS-NEXT: lui a4, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: li a5, 48
-; RV64IA-WMO-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a6, a3
-; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB117_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-WMO-NOZACAS-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB117_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_min_i16_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NOZACAS-NEXT: lui a4, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: li a5, 48
-; RV64IA-TSO-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a6, a3
-; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB117_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-TSO-NOZACAS-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB117_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i16_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: li a5, 48
-; RV64IA-WMO-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a6, a3
-; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB117_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-WMO-ZACAS-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB117_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_min_i16_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: li a5, 48
-; RV64IA-TSO-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a6, a3
-; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB117_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-TSO-ZACAS-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB117_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomin.h.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_min_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NEXT: lui a4, 16
+; RV64IA-WMO-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srai a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: li a5, 48
+; RV64IA-WMO-NEXT: sub a5, a5, a3
+; RV64IA-WMO-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NEXT: and a7, a3, a4
+; RV64IA-WMO-NEXT: mv a6, a3
+; RV64IA-WMO-NEXT: sll a7, a7, a5
+; RV64IA-WMO-NEXT: sra a7, a7, a5
+; RV64IA-WMO-NEXT: bge a1, a7, .LBB117_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1
+; RV64IA-WMO-NEXT: xor a6, a3, a1
+; RV64IA-WMO-NEXT: and a6, a6, a4
+; RV64IA-WMO-NEXT: xor a6, a3, a6
+; RV64IA-WMO-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NEXT: bnez a6, .LBB117_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_min_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NEXT: lui a4, 16
+; RV64IA-TSO-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srai a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: li a5, 48
+; RV64IA-TSO-NEXT: sub a5, a5, a3
+; RV64IA-TSO-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a7, a3, a4
+; RV64IA-TSO-NEXT: mv a6, a3
+; RV64IA-TSO-NEXT: sll a7, a7, a5
+; RV64IA-TSO-NEXT: sra a7, a7, a5
+; RV64IA-TSO-NEXT: bge a1, a7, .LBB117_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1
+; RV64IA-TSO-NEXT: xor a6, a3, a1
+; RV64IA-TSO-NEXT: and a6, a6, a4
+; RV64IA-TSO-NEXT: xor a6, a3, a6
+; RV64IA-TSO-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NEXT: bnez a6, .LBB117_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b release
ret i16 %1
}
@@ -17509,139 +12036,67 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NOZACAS-NEXT: lui a4, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: li a5, 48
-; RV64IA-WMO-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a6, a3
-; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB118_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-WMO-NOZACAS-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB118_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_min_i16_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NOZACAS-NEXT: lui a4, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: li a5, 48
-; RV64IA-TSO-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a6, a3
-; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB118_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-TSO-NOZACAS-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB118_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i16_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: li a5, 48
-; RV64IA-WMO-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-WMO-ZACAS-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a6, a3
-; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB118_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-WMO-ZACAS-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB118_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_min_i16_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: li a5, 48
-; RV64IA-TSO-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-TSO-ZACAS-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a6, a3
-; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB118_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-TSO-ZACAS-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB118_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomin.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_min_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NEXT: lui a4, 16
+; RV64IA-WMO-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NEXT: srai a1, a1, 48
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: li a5, 48
+; RV64IA-WMO-NEXT: sub a5, a5, a3
+; RV64IA-WMO-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: and a7, a3, a4
+; RV64IA-WMO-NEXT: mv a6, a3
+; RV64IA-WMO-NEXT: sll a7, a7, a5
+; RV64IA-WMO-NEXT: sra a7, a7, a5
+; RV64IA-WMO-NEXT: bge a1, a7, .LBB118_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1
+; RV64IA-WMO-NEXT: xor a6, a3, a1
+; RV64IA-WMO-NEXT: and a6, a6, a4
+; RV64IA-WMO-NEXT: xor a6, a3, a6
+; RV64IA-WMO-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NEXT: bnez a6, .LBB118_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_min_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NEXT: lui a4, 16
+; RV64IA-TSO-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NEXT: srai a1, a1, 48
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: li a5, 48
+; RV64IA-TSO-NEXT: sub a5, a5, a3
+; RV64IA-TSO-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a7, a3, a4
+; RV64IA-TSO-NEXT: mv a6, a3
+; RV64IA-TSO-NEXT: sll a7, a7, a5
+; RV64IA-TSO-NEXT: sra a7, a7, a5
+; RV64IA-TSO-NEXT: bge a1, a7, .LBB118_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1
+; RV64IA-TSO-NEXT: xor a6, a3, a1
+; RV64IA-TSO-NEXT: and a6, a6, a4
+; RV64IA-TSO-NEXT: xor a6, a3, a6
+; RV64IA-TSO-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NEXT: bnez a6, .LBB118_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -17762,77 +12217,36 @@ define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_min_i16_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
-; RV64IA-NOZACAS-NEXT: lui a4, 16
-; RV64IA-NOZACAS-NEXT: addi a4, a4, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-NOZACAS-NEXT: slli a1, a1, 48
-; RV64IA-NOZACAS-NEXT: srai a1, a1, 48
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: li a5, 48
-; RV64IA-NOZACAS-NEXT: sub a5, a5, a3
-; RV64IA-NOZACAS-NEXT: .LBB119_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NOZACAS-NEXT: and a7, a3, a4
-; RV64IA-NOZACAS-NEXT: mv a6, a3
-; RV64IA-NOZACAS-NEXT: sll a7, a7, a5
-; RV64IA-NOZACAS-NEXT: sra a7, a7, a5
-; RV64IA-NOZACAS-NEXT: bge a1, a7, .LBB119_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB119_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a6, a3, a1
-; RV64IA-NOZACAS-NEXT: and a6, a6, a4
-; RV64IA-NOZACAS-NEXT: xor a6, a3, a6
-; RV64IA-NOZACAS-NEXT: .LBB119_3: # in Loop: Header=BB119_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a6, .LBB119_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_min_i16_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: andi a3, a0, 24
-; RV64IA-ZACAS-NEXT: lui a4, 16
-; RV64IA-ZACAS-NEXT: addi a4, a4, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
-; RV64IA-ZACAS-NEXT: slli a1, a1, 48
-; RV64IA-ZACAS-NEXT: srai a1, a1, 48
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: li a5, 48
-; RV64IA-ZACAS-NEXT: sub a5, a5, a3
-; RV64IA-ZACAS-NEXT: .LBB119_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-ZACAS-NEXT: and a7, a3, a4
-; RV64IA-ZACAS-NEXT: mv a6, a3
-; RV64IA-ZACAS-NEXT: sll a7, a7, a5
-; RV64IA-ZACAS-NEXT: sra a7, a7, a5
-; RV64IA-ZACAS-NEXT: bge a1, a7, .LBB119_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB119_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a6, a3, a1
-; RV64IA-ZACAS-NEXT: and a6, a6, a4
-; RV64IA-ZACAS-NEXT: xor a6, a3, a6
-; RV64IA-ZACAS-NEXT: .LBB119_3: # in Loop: Header=BB119_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-ZACAS-NEXT: bnez a6, .LBB119_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomin.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_min_i16_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: andi a3, a0, 24
+; RV64IA-NEXT: lui a4, 16
+; RV64IA-NEXT: addi a4, a4, -1
+; RV64IA-NEXT: sllw a4, a4, a0
+; RV64IA-NEXT: slli a1, a1, 48
+; RV64IA-NEXT: srai a1, a1, 48
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: li a5, 48
+; RV64IA-NEXT: sub a5, a5, a3
+; RV64IA-NEXT: .LBB119_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NEXT: and a7, a3, a4
+; RV64IA-NEXT: mv a6, a3
+; RV64IA-NEXT: sll a7, a7, a5
+; RV64IA-NEXT: sra a7, a7, a5
+; RV64IA-NEXT: bge a1, a7, .LBB119_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB119_1 Depth=1
+; RV64IA-NEXT: xor a6, a3, a1
+; RV64IA-NEXT: and a6, a6, a4
+; RV64IA-NEXT: xor a6, a3, a6
+; RV64IA-NEXT: .LBB119_3: # in Loop: Header=BB119_1 Depth=1
+; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-NEXT: bnez a6, .LBB119_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -17951,65 +12365,30 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i16_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB120_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-NOZACAS-NEXT: mv a5, a3
-; RV64IA-NOZACAS-NEXT: bgeu a6, a1, .LBB120_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB120_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: .LBB120_3: # in Loop: Header=BB120_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB120_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_umax_i16_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a3, 16
-; RV64IA-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB120_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-ZACAS-NEXT: mv a5, a3
-; RV64IA-ZACAS-NEXT: bgeu a6, a1, .LBB120_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB120_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: .LBB120_3: # in Loop: Header=BB120_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB120_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomaxu.h a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_umax_i16_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addi a3, a3, -1
+; RV64IA-NEXT: sllw a4, a3, a0
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB120_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a3, (a2)
+; RV64IA-NEXT: and a6, a3, a4
+; RV64IA-NEXT: mv a5, a3
+; RV64IA-NEXT: bgeu a6, a1, .LBB120_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB120_1 Depth=1
+; RV64IA-NEXT: xor a5, a3, a1
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: .LBB120_3: # in Loop: Header=BB120_1 Depth=1
+; RV64IA-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB120_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -18153,115 +12532,55 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB121_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB121_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i16_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB121_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB121_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i16_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a3
-; RV64IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB121_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB121_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umax_i16_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a3
-; RV64IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB121_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB121_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomaxu.h.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umax_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: and a6, a3, a4
+; RV64IA-WMO-NEXT: mv a5, a3
+; RV64IA-WMO-NEXT: bgeu a6, a1, .LBB121_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a3, a1
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB121_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_umax_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a6, a3, a4
+; RV64IA-TSO-NEXT: mv a5, a3
+; RV64IA-TSO-NEXT: bgeu a6, a1, .LBB121_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a3, a1
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB121_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b acquire
ret i16 %1
}
@@ -18405,115 +12724,55 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB122_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB122_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i16_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB122_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB122_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i16_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a3
-; RV64IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB122_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB122_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umax_i16_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a3
-; RV64IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB122_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB122_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomaxu.h.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umax_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NEXT: and a6, a3, a4
+; RV64IA-WMO-NEXT: mv a5, a3
+; RV64IA-WMO-NEXT: bgeu a6, a1, .LBB122_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a3, a1
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB122_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_umax_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a6, a3, a4
+; RV64IA-TSO-NEXT: mv a5, a3
+; RV64IA-TSO-NEXT: bgeu a6, a1, .LBB122_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a3, a1
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB122_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b release
ret i16 %1
}
@@ -18657,115 +12916,55 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB123_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB123_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i16_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB123_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB123_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i16_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a3
-; RV64IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB123_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB123_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umax_i16_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a3
-; RV64IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB123_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB123_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomaxu.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umax_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: and a6, a3, a4
+; RV64IA-WMO-NEXT: mv a5, a3
+; RV64IA-WMO-NEXT: bgeu a6, a1, .LBB123_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a3, a1
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB123_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_umax_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a6, a3, a4
+; RV64IA-TSO-NEXT: mv a5, a3
+; RV64IA-TSO-NEXT: bgeu a6, a1, .LBB123_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a3, a1
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB123_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -18884,65 +13083,30 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i16_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB124_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-NOZACAS-NEXT: mv a5, a3
-; RV64IA-NOZACAS-NEXT: bgeu a6, a1, .LBB124_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB124_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: .LBB124_3: # in Loop: Header=BB124_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB124_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_umax_i16_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a3, 16
-; RV64IA-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB124_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-ZACAS-NEXT: mv a5, a3
-; RV64IA-ZACAS-NEXT: bgeu a6, a1, .LBB124_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB124_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: .LBB124_3: # in Loop: Header=BB124_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB124_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amomaxu.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_umax_i16_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addi a3, a3, -1
+; RV64IA-NEXT: sllw a4, a3, a0
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB124_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NEXT: and a6, a3, a4
+; RV64IA-NEXT: mv a5, a3
+; RV64IA-NEXT: bgeu a6, a1, .LBB124_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB124_1 Depth=1
+; RV64IA-NEXT: xor a5, a3, a1
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: .LBB124_3: # in Loop: Header=BB124_1 Depth=1
+; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB124_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -19061,65 +13225,30 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i16_monotonic:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB125_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-NOZACAS-NEXT: mv a5, a3
-; RV64IA-NOZACAS-NEXT: bgeu a1, a6, .LBB125_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB125_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: .LBB125_3: # in Loop: Header=BB125_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB125_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_umin_i16_monotonic:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a3, 16
-; RV64IA-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB125_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-ZACAS-NEXT: mv a5, a3
-; RV64IA-ZACAS-NEXT: bgeu a1, a6, .LBB125_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB125_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: .LBB125_3: # in Loop: Header=BB125_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB125_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_monotonic:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amominu.h a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_monotonic:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_umin_i16_monotonic:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addi a3, a3, -1
+; RV64IA-NEXT: sllw a4, a3, a0
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB125_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w a3, (a2)
+; RV64IA-NEXT: and a6, a3, a4
+; RV64IA-NEXT: mv a5, a3
+; RV64IA-NEXT: bgeu a1, a6, .LBB125_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB125_1 Depth=1
+; RV64IA-NEXT: xor a5, a3, a1
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: .LBB125_3: # in Loop: Header=BB125_1 Depth=1
+; RV64IA-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB125_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -19263,115 +13392,55 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_acquire:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB126_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB126_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i16_acquire:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB126_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB126_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i16_acquire:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a3
-; RV64IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB126_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB126_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umin_i16_acquire:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a3
-; RV64IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB126_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB126_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_acquire:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amominu.h.aq a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umin_i16_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: and a6, a3, a4
+; RV64IA-WMO-NEXT: mv a5, a3
+; RV64IA-WMO-NEXT: bgeu a1, a6, .LBB126_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a3, a1
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB126_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_acquire:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_umin_i16_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a6, a3, a4
+; RV64IA-TSO-NEXT: mv a5, a3
+; RV64IA-TSO-NEXT: bgeu a1, a6, .LBB126_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a3, a1
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB126_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b acquire
ret i16 %1
}
@@ -19515,115 +13584,55 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_release:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB127_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB127_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i16_release:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB127_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB127_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i16_release:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a3
-; RV64IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB127_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB127_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umin_i16_release:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a3
-; RV64IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB127_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB127_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_release:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amominu.h.rl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umin_i16_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NEXT: and a6, a3, a4
+; RV64IA-WMO-NEXT: mv a5, a3
+; RV64IA-WMO-NEXT: bgeu a1, a6, .LBB127_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a3, a1
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB127_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_release:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_umin_i16_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a6, a3, a4
+; RV64IA-TSO-NEXT: mv a5, a3
+; RV64IA-TSO-NEXT: bgeu a1, a6, .LBB127_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a3, a1
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB127_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b release
ret i16 %1
}
@@ -19767,115 +13776,55 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_acq_rel:
-; RV64IA-WMO-NOZACAS: # %bb.0:
-; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NOZACAS-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-WMO-NOZACAS-NEXT: mv a5, a3
-; RV64IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB128_3
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NOZACAS-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1
-; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB128_1
-; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i16_acq_rel:
-; RV64IA-TSO-NOZACAS: # %bb.0:
-; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NOZACAS-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-TSO-NOZACAS-NEXT: mv a5, a3
-; RV64IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB128_3
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NOZACAS-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1
-; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB128_1
-; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i16_acq_rel:
-; RV64IA-WMO-ZACAS: # %bb.0:
-; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
-; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-ZACAS-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-WMO-ZACAS-NEXT: mv a5, a3
-; RV64IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB128_3
-; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-WMO-ZACAS-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1
-; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB128_1
-; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
-; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umin_i16_acq_rel:
-; RV64IA-TSO-ZACAS: # %bb.0:
-; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
-; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-ZACAS-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-TSO-ZACAS-NEXT: mv a5, a3
-; RV64IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB128_3
-; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-TSO-ZACAS-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1
-; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB128_1
-; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
-; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_acq_rel:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amominu.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_umin_i16_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a3, 16
+; RV64IA-WMO-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NEXT: and a1, a1, a3
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NEXT: and a6, a3, a4
+; RV64IA-WMO-NEXT: mv a5, a3
+; RV64IA-WMO-NEXT: bgeu a1, a6, .LBB128_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a3, a1
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NEXT: bnez a5, .LBB128_1
+; RV64IA-WMO-NEXT: # %bb.4:
+; RV64IA-WMO-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NEXT: ret
;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_acq_rel:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-TSO-LABEL: atomicrmw_umin_i16_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a3, 16
+; RV64IA-TSO-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NEXT: and a1, a1, a3
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NEXT: and a6, a3, a4
+; RV64IA-TSO-NEXT: mv a5, a3
+; RV64IA-TSO-NEXT: bgeu a1, a6, .LBB128_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a3, a1
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NEXT: bnez a5, .LBB128_1
+; RV64IA-TSO-NEXT: # %bb.4:
+; RV64IA-TSO-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -19994,65 +13943,30 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i16_seq_cst:
-; RV64IA-NOZACAS: # %bb.0:
-; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
-; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
-; RV64IA-NOZACAS-NEXT: lui a3, 16
-; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
-; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-NOZACAS-NEXT: and a1, a1, a3
-; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-NOZACAS-NEXT: .LBB129_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NOZACAS-NEXT: and a6, a3, a4
-; RV64IA-NOZACAS-NEXT: mv a5, a3
-; RV64IA-NOZACAS-NEXT: bgeu a1, a6, .LBB129_3
-; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB129_1 Depth=1
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a1
-; RV64IA-NOZACAS-NEXT: and a5, a5, a4
-; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
-; RV64IA-NOZACAS-NEXT: .LBB129_3: # in Loop: Header=BB129_1 Depth=1
-; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NOZACAS-NEXT: bnez a5, .LBB129_1
-; RV64IA-NOZACAS-NEXT: # %bb.4:
-; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-NOZACAS-NEXT: ret
-;
-; RV64IA-ZACAS-LABEL: atomicrmw_umin_i16_seq_cst:
-; RV64IA-ZACAS: # %bb.0:
-; RV64IA-ZACAS-NEXT: andi a2, a0, -4
-; RV64IA-ZACAS-NEXT: slli a0, a0, 3
-; RV64IA-ZACAS-NEXT: lui a3, 16
-; RV64IA-ZACAS-NEXT: addi a3, a3, -1
-; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
-; RV64IA-ZACAS-NEXT: and a1, a1, a3
-; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
-; RV64IA-ZACAS-NEXT: .LBB129_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-ZACAS-NEXT: and a6, a3, a4
-; RV64IA-ZACAS-NEXT: mv a5, a3
-; RV64IA-ZACAS-NEXT: bgeu a1, a6, .LBB129_3
-; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB129_1 Depth=1
-; RV64IA-ZACAS-NEXT: xor a5, a3, a1
-; RV64IA-ZACAS-NEXT: and a5, a5, a4
-; RV64IA-ZACAS-NEXT: xor a5, a3, a5
-; RV64IA-ZACAS-NEXT: .LBB129_3: # in Loop: Header=BB129_1 Depth=1
-; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-ZACAS-NEXT: bnez a5, .LBB129_1
-; RV64IA-ZACAS-NEXT: # %bb.4:
-; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
-; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_seq_cst:
-; RV64IA-WMO-ZABHA: # %bb.0:
-; RV64IA-WMO-ZABHA-NEXT: amominu.h.aqrl a0, a1, (a0)
-; RV64IA-WMO-ZABHA-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_seq_cst:
-; RV64IA-TSO-ZABHA: # %bb.0:
-; RV64IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0)
-; RV64IA-TSO-ZABHA-NEXT: ret
+; RV64IA-LABEL: atomicrmw_umin_i16_seq_cst:
+; RV64IA: # %bb.0:
+; RV64IA-NEXT: andi a2, a0, -4
+; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: lui a3, 16
+; RV64IA-NEXT: addi a3, a3, -1
+; RV64IA-NEXT: sllw a4, a3, a0
+; RV64IA-NEXT: and a1, a1, a3
+; RV64IA-NEXT: sllw a1, a1, a0
+; RV64IA-NEXT: .LBB129_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NEXT: and a6, a3, a4
+; RV64IA-NEXT: mv a5, a3
+; RV64IA-NEXT: bgeu a1, a6, .LBB129_3
+; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB129_1 Depth=1
+; RV64IA-NEXT: xor a5, a3, a1
+; RV64IA-NEXT: and a5, a5, a4
+; RV64IA-NEXT: xor a5, a3, a5
+; RV64IA-NEXT: .LBB129_3: # in Loop: Header=BB129_1 Depth=1
+; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NEXT: bnez a5, .LBB129_1
+; RV64IA-NEXT: # %bb.4:
+; RV64IA-NEXT: srlw a0, a3, a0
+; RV64IA-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -20987,58 +14901,6 @@ define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64IA-ZACAS-NEXT: bne a0, a3, .LBB150_1
; RV64IA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_monotonic:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB150_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_monotonic:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB150_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_monotonic:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB150_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB150_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_monotonic:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB150_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB150_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i32 %b monotonic
ret i32 %1
}
@@ -21167,58 +15029,6 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB151_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_acquire:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a2, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB151_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_acquire:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB151_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_acquire:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB151_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.w.aq a0, a4, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB151_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_acquire:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB151_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB151_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i32 %b acquire
ret i32 %1
}
@@ -21347,58 +15157,6 @@ define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB152_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_release:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a3, a3, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB152_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_release:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB152_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_release:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB152_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.w.rl a0, a4, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB152_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_release:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB152_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB152_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i32 %b release
ret i32 %1
}
@@ -21527,58 +15285,6 @@ define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB153_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_acq_rel:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a2, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a3, a3, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB153_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_acq_rel:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB153_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_acq_rel:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB153_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.w.aqrl a0, a4, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB153_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_acq_rel:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB153_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB153_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i32 %b acq_rel
ret i32 %1
}
@@ -21683,58 +15389,6 @@ define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB154_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_seq_cst:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a2, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a3, a3, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB154_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_seq_cst:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a2, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w.rl a3, a3, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB154_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_seq_cst:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB154_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.w.aqrl a0, a4, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB154_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_seq_cst:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB154_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB154_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i32 %b seq_cst
ret i32 %1
}
@@ -25024,58 +18678,6 @@ define i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64IA-ZACAS-NEXT: bne a0, a3, .LBB205_1
; RV64IA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_monotonic:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB205_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.d a2, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.d a3, a3, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB205_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_monotonic:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB205_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.d a2, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.d a3, a3, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB205_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_monotonic:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB205_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.d a0, a4, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB205_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_monotonic:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB205_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.d a0, a4, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB205_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i64 %b monotonic
ret i64 %1
}
@@ -25162,58 +18764,6 @@ define i64 @atomicrmw_nand_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB206_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_acquire:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB206_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.d.aq a2, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.d a3, a3, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB206_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_acquire:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB206_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.d a2, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.d a3, a3, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB206_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_acquire:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB206_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.d.aq a0, a4, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB206_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_acquire:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB206_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.d a0, a4, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB206_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i64 %b acquire
ret i64 %1
}
@@ -25300,58 +18850,6 @@ define i64 @atomicrmw_nand_i64_release(ptr %a, i64 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB207_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_release:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB207_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.d a2, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.d.rl a3, a3, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB207_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_release:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB207_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.d a2, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.d a3, a3, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB207_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_release:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB207_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.d.rl a0, a4, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB207_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_release:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB207_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.d a0, a4, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB207_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i64 %b release
ret i64 %1
}
@@ -25438,58 +18936,6 @@ define i64 @atomicrmw_nand_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB208_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_acq_rel:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB208_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.d.aq a2, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.d.rl a3, a3, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB208_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_acq_rel:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB208_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.d a2, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.d a3, a3, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB208_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_acq_rel:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB208_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.d.aqrl a0, a4, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB208_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_acq_rel:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB208_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.d a0, a4, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB208_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i64 %b acq_rel
ret i64 %1
}
@@ -25564,58 +19010,6 @@ define i64 @atomicrmw_nand_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB209_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_seq_cst:
-; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB209_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.d.aqrl a2, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.d.rl a3, a3, (a0)
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB209_1
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_seq_cst:
-; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB209_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.d.aqrl a2, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.d.rl a3, a3, (a0)
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB209_1
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
-; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
-;
-; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_seq_cst:
-; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB209_1: # %atomicrmw.start
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.d.aqrl a0, a4, (a2)
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB209_1
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
-;
-; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_seq_cst:
-; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB209_1: # %atomicrmw.start
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.d a0, a4, (a2)
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB209_1
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
-; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i64 %b seq_cst
ret i64 %1
}
diff --git a/llvm/test/Transforms/InstCombine/fsh.ll b/llvm/test/Transforms/InstCombine/fsh.ll
index 6c85169453d15a..48bf296993f6ac 100644
--- a/llvm/test/Transforms/InstCombine/fsh.ll
+++ b/llvm/test/Transforms/InstCombine/fsh.ll
@@ -722,134 +722,6 @@ define i32 @fsh_orconst_rotate(i32 %a) {
ret i32 %t2
}
-define i32 @fsh_rotate_5(i8 %x, i32 %y) {
-; CHECK-LABEL: @fsh_rotate_5(
-; CHECK-NEXT: [[T1:%.*]] = zext i8 [[X:%.*]] to i32
-; CHECK-NEXT: [[OR1:%.*]] = or i32 [[T1]], [[Y:%.*]]
-; CHECK-NEXT: [[OR2:%.*]] = call i32 @llvm.fshl.i32(i32 [[OR1]], i32 [[OR1]], i32 5)
-; CHECK-NEXT: ret i32 [[OR2]]
-;
-
- %t1 = zext i8 %x to i32
- %or1 = or i32 %t1, %y
- %shr = lshr i32 %or1, 27
- %shl = shl i32 %or1, 5
- %or2 = or i32 %shr, %shl
- ret i32 %or2
-}
-
-define i32 @fsh_rotate_18(i8 %x, i32 %y) {
-; CHECK-LABEL: @fsh_rotate_18(
-; CHECK-NEXT: [[T1:%.*]] = zext i8 [[X:%.*]] to i32
-; CHECK-NEXT: [[OR1:%.*]] = or i32 [[T1]], [[Y:%.*]]
-; CHECK-NEXT: [[OR2:%.*]] = call i32 @llvm.fshl.i32(i32 [[OR1]], i32 [[OR1]], i32 18)
-; CHECK-NEXT: ret i32 [[OR2]]
-;
-
- %t1 = zext i8 %x to i32
- %or1 = or i32 %t1, %y
- %shr = lshr i32 %or1, 14
- %shl = shl i32 %or1, 18
- %or2 = or i32 %shr, %shl
- ret i32 %or2
-}
-
-define i32 @fsh_load_rotate_12(ptr %data) {
-; CHECK-LABEL: @fsh_load_rotate_12(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[DATA:%.*]], align 1
-; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
-; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[CONV]], 24
-; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 1
-; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1
-; CHECK-NEXT: [[CONV2:%.*]] = zext i8 [[TMP1]] to i32
-; CHECK-NEXT: [[SHL3:%.*]] = shl nuw nsw i32 [[CONV2]], 16
-; CHECK-NEXT: [[OR:%.*]] = or disjoint i32 [[SHL3]], [[SHL]]
-; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 2
-; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
-; CHECK-NEXT: [[CONV5:%.*]] = zext i8 [[TMP2]] to i32
-; CHECK-NEXT: [[SHL6:%.*]] = shl nuw nsw i32 [[CONV5]], 8
-; CHECK-NEXT: [[OR7:%.*]] = or disjoint i32 [[OR]], [[SHL6]]
-; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 3
-; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1
-; CHECK-NEXT: [[CONV9:%.*]] = zext i8 [[TMP3]] to i32
-; CHECK-NEXT: [[OR10:%.*]] = or disjoint i32 [[OR7]], [[CONV9]]
-; CHECK-NEXT: [[OR15:%.*]] = call i32 @llvm.fshl.i32(i32 [[OR10]], i32 [[OR10]], i32 12)
-; CHECK-NEXT: ret i32 [[OR15]]
-;
-
-entry:
- %0 = load i8, ptr %data
- %conv = zext i8 %0 to i32
- %shl = shl nuw i32 %conv, 24
- %arrayidx1 = getelementptr inbounds i8, ptr %data, i64 1
- %1 = load i8, ptr %arrayidx1
- %conv2 = zext i8 %1 to i32
- %shl3 = shl nuw nsw i32 %conv2, 16
- %or = or i32 %shl3, %shl
- %arrayidx4 = getelementptr inbounds i8, ptr %data, i64 2
- %2 = load i8, ptr %arrayidx4
- %conv5 = zext i8 %2 to i32
- %shl6 = shl nuw nsw i32 %conv5, 8
- %or7 = or i32 %or, %shl6
- %arrayidx8 = getelementptr inbounds i8, ptr %data, i64 3
- %3 = load i8, ptr %arrayidx8
- %conv9 = zext i8 %3 to i32
- %or10 = or i32 %or7, %conv9
- %shr = lshr i32 %or10, 20
- %shl7 = shl i32 %or10, 12
- %or15 = or i32 %shr, %shl7
- ret i32 %or15
-}
-
-define i32 @fsh_load_rotate_25(ptr %data) {
-; CHECK-LABEL: @fsh_load_rotate_25(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[DATA:%.*]], align 1
-; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
-; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[CONV]], 24
-; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 1
-; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1
-; CHECK-NEXT: [[CONV2:%.*]] = zext i8 [[TMP1]] to i32
-; CHECK-NEXT: [[SHL3:%.*]] = shl nuw nsw i32 [[CONV2]], 16
-; CHECK-NEXT: [[OR:%.*]] = or disjoint i32 [[SHL3]], [[SHL]]
-; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 2
-; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
-; CHECK-NEXT: [[CONV5:%.*]] = zext i8 [[TMP2]] to i32
-; CHECK-NEXT: [[SHL6:%.*]] = shl nuw nsw i32 [[CONV5]], 8
-; CHECK-NEXT: [[OR7:%.*]] = or disjoint i32 [[OR]], [[SHL6]]
-; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 3
-; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1
-; CHECK-NEXT: [[CONV9:%.*]] = zext i8 [[TMP3]] to i32
-; CHECK-NEXT: [[OR10:%.*]] = or disjoint i32 [[OR7]], [[CONV9]]
-; CHECK-NEXT: [[OR15:%.*]] = call i32 @llvm.fshl.i32(i32 [[OR10]], i32 [[OR10]], i32 25)
-; CHECK-NEXT: ret i32 [[OR15]]
-;
-
-entry:
- %0 = load i8, ptr %data
- %conv = zext i8 %0 to i32
- %shl = shl nuw i32 %conv, 24
- %arrayidx1 = getelementptr inbounds i8, ptr %data, i64 1
- %1 = load i8, ptr %arrayidx1
- %conv2 = zext i8 %1 to i32
- %shl3 = shl nuw nsw i32 %conv2, 16
- %or = or i32 %shl3, %shl
- %arrayidx4 = getelementptr inbounds i8, ptr %data, i64 2
- %2 = load i8, ptr %arrayidx4
- %conv5 = zext i8 %2 to i32
- %shl6 = shl nuw nsw i32 %conv5, 8
- %or7 = or i32 %or, %shl6
- %arrayidx8 = getelementptr inbounds i8, ptr %data, i64 3
- %3 = load i8, ptr %arrayidx8
- %conv9 = zext i8 %3 to i32
- %or10 = or i32 %or7, %conv9
- %shr = lshr i32 %or10, 7
- %shl7 = shl i32 %or10, 25
- %or15 = or i32 %shr, %shl7
- ret i32 %or15
-}
-
define <2 x i31> @fshr_mask_args_same_vector(<2 x i31> %a) {
; CHECK-LABEL: @fshr_mask_args_same_vector(
; CHECK-NEXT: [[T3:%.*]] = shl <2 x i31> [[A:%.*]], <i31 10, i31 10>
diff --git a/llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll b/llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll
index 996d2c0e67e165..1042c413fbb7bb 100644
--- a/llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll
+++ b/llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll
@@ -38,8 +38,8 @@ define ptr @test2() {
define void @test3_multiple_fields(ptr nocapture %a, ptr nocapture %b) {
; CHECK-LABEL: @test3_multiple_fields(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[B:%.*]], align 4, !tbaa.struct [[TBAA_STRUCT3:![0-9]+]]
-; CHECK-NEXT: store i64 [[TMP0]], ptr [[A:%.*]], align 4, !tbaa.struct [[TBAA_STRUCT3]]
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[B:%.*]], align 4
+; CHECK-NEXT: store i64 [[TMP0]], ptr [[A:%.*]], align 4
; CHECK-NEXT: ret void
;
entry:
@@ -86,5 +86,4 @@ entry:
; CHECK: [[TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}
; CHECK: [[META1]] = !{!"float", [[META2:![0-9]+]]}
; CHECK: [[META2]] = !{!"Simple C/C++ TBAA"}
-; CHECK: [[TBAA_STRUCT3]] = !{i64 0, i64 4, [[TBAA0]], i64 4, i64 4, [[TBAA0]]}
;.
diff --git a/llvm/test/Transforms/LoopRotate/coroutine.ll b/llvm/test/Transforms/LoopRotate/coroutine.ll
new file mode 100644
index 00000000000000..b035b51da1dffc
--- /dev/null
+++ b/llvm/test/Transforms/LoopRotate/coroutine.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -S -passes=loop-rotate < %s | FileCheck %s
+
+declare void @bar1()
+
+ at threadlocalint = thread_local global i32 0, align 4
+
+define void @foo() #0 {
+; CHECK-LABEL: define void @foo(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @threadlocalint)
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
+; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT: br i1 [[CMP1]], label [[COND_END_LR_PH:%.*]], label [[COND_FALSE:%.*]]
+; CHECK: cond.end.lr.ph:
+; CHECK-NEXT: br label [[COND_END:%.*]]
+; CHECK: while.cond.cond.false_crit_edge:
+; CHECK-NEXT: br label [[COND_FALSE]]
+; CHECK: cond.false:
+; CHECK-NEXT: call void @bar1()
+; CHECK-NEXT: unreachable
+; CHECK: cond.end:
+; CHECK-NEXT: call void @bar1()
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP2]], 0
+; CHECK-NEXT: br i1 [[CMP]], label [[COND_END]], label [[WHILE_COND_COND_FALSE_CRIT_EDGE:%.*]]
+;
+entry:
+ br label %while.cond
+
+while.cond:
+ %1 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @threadlocalint)
+ %2 = load i32, ptr %1, align 4
+ %cmp = icmp eq i32 %2, 0
+ br i1 %cmp, label %cond.end, label %cond.false
+
+cond.false:
+ call void @bar1()
+ unreachable
+
+cond.end:
+ call void @bar1()
+ br label %while.cond
+}
+
+attributes #0 = { presplitcoroutine }
diff --git a/llvm/test/Transforms/LoopVectorize/trunc-reductions.ll b/llvm/test/Transforms/LoopVectorize/trunc-reductions.ll
index debb26b6329b71..2278821c5b2f9c 100644
--- a/llvm/test/Transforms/LoopVectorize/trunc-reductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/trunc-reductions.ll
@@ -245,68 +245,3 @@ for.end:
%ret = trunc i32 %min to i16
ret i16 %ret
}
-
-; Test case for https://github.com/llvm/llvm-project/issues/81415.
-define i32 @reduction_and_or(i16 %a, i32 %b, ptr %src) {
-; CHECK-LABEL: @reduction_and_or(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
-; CHECK: vector.ph:
-; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
-; CHECK: vector.body:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <8 x i32> [ <i32 10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, [[VECTOR_PH]] ], [ [[TMP2:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[INDEX]] to i64
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC:%.*]], i64 [[TMP0]]
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP2]] = or <8 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
-; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 992
-; CHECK-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
-; CHECK: middle.block:
-; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> [[TMP2]])
-; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]]
-; CHECK: scalar.ph:
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[TMP4]], [[MIDDLE_BLOCK]] ]
-; CHECK-NEXT: br label [[LOOP:%.*]]
-; CHECK: loop:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 992, [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[OR67:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[OR:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[TMP5:%.*]] = zext nneg i32 [[IV]] to i64
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP5]]
-; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP]], align 4
-; CHECK-NEXT: [[OR]] = or i32 [[OR67]], [[L]]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], 999
-; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
-; CHECK: exit:
-; CHECK-NEXT: [[OR_LCSSA:%.*]] = phi i32 [ [[OR]], [[LOOP]] ], [ poison, [[MIDDLE_BLOCK]] ]
-; CHECK-NEXT: ret i32 [[OR_LCSSA]]
-;
-entry:
- %ext1 = zext i16 %a to i32
- br label %loop
-
-loop:
- %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
- %or67 = phi i32 [ 10, %entry ], [ %or, %loop ]
- %t = trunc i32 %b to i16
- %ext = sext i16 %t to i32
- %cmp = icmp sgt i32 %ext, %ext1
- %ext2 = zext i1 %cmp to i32
- %cmp3 = icmp sge i32 %iv, %ext2
- %ext4 = zext i1 %cmp3 to i32
- %div = sdiv i32 %ext4, %b
- %and = and i32 %div, 0
- %gep = getelementptr inbounds i32, ptr %src, i32 %iv
- %l = load i32, ptr %gep
- %add = add i32 %and, %l
- %or = or i32 %or67, %add
- %iv.next = add nsw i32 %iv, 1
- %tobool.not = icmp eq i32 %iv.next, 999
- br i1 %tobool.not, label %exit, label %loop
-
-exit:
- %or.lcssa = phi i32 [ %or, %loop ]
- ret i32 %or.lcssa
-}
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/horizontal.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/horizontal.ll
index 1986b51ec94828..e0aa038005944c 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/horizontal.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/horizontal.ll
@@ -32,14 +32,14 @@ define i32 @test_select(ptr noalias nocapture readonly %blk1, ptr noalias nocapt
; CHECK-NEXT: [[J_025:%.*]] = phi i32 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[P2_024:%.*]] = phi ptr [ [[BLK2:%.*]], [[FOR_BODY_LR_PH]] ], [ [[ADD_PTR29:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[P1_023:%.*]] = phi ptr [ [[BLK1:%.*]], [[FOR_BODY_LR_PH]] ], [ [[ADD_PTR:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[P1_023]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P2_024]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = sub nsw <4 x i32> [[TMP0]], [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <4 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = sub nsw <4 x i32> zeroinitializer, [[TMP2]]
-; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> [[TMP2]]
-; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP5]])
-; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP6]], [[S_026]]
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P1_023]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[P2_024]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = sub nsw <4 x i32> [[TMP1]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp slt <4 x i32> [[TMP4]], zeroinitializer
+; CHECK-NEXT: [[TMP6:%.*]] = sub nsw <4 x i32> zeroinitializer, [[TMP4]]
+; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[TMP6]], <4 x i32> [[TMP4]]
+; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP7]])
+; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP8]], [[S_026]]
; CHECK-NEXT: [[ADD_PTR]] = getelementptr inbounds i32, ptr [[P1_023]], i64 [[IDX_EXT]]
; CHECK-NEXT: [[ADD_PTR29]] = getelementptr inbounds i32, ptr [[P2_024]], i64 [[IDX_EXT]]
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[J_025]], 1
@@ -150,11 +150,11 @@ define i32 @reduction_with_br(ptr noalias nocapture readonly %blk1, ptr noalias
; CHECK-NEXT: [[J_019:%.*]] = phi i32 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[IF_END]] ]
; CHECK-NEXT: [[P2_018:%.*]] = phi ptr [ [[BLK2:%.*]], [[FOR_BODY_LR_PH]] ], [ [[ADD_PTR16:%.*]], [[IF_END]] ]
; CHECK-NEXT: [[P1_017:%.*]] = phi ptr [ [[BLK1:%.*]], [[FOR_BODY_LR_PH]] ], [ [[ADD_PTR:%.*]], [[IF_END]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[P1_017]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P2_018]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = mul nsw <4 x i32> [[TMP1]], [[TMP0]]
-; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])
-; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP3]], [[S_020]]
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P1_017]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[P2_018]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = mul nsw <4 x i32> [[TMP3]], [[TMP1]]
+; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP4]])
+; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP5]], [[S_020]]
; CHECK-NEXT: [[CMP14:%.*]] = icmp slt i32 [[OP_RDX]], [[LIM:%.*]]
; CHECK-NEXT: br i1 [[CMP14]], label [[IF_END]], label [[FOR_END_LOOPEXIT:%.*]]
; CHECK: if.end:
@@ -245,16 +245,16 @@ define i32 @test_unrolled_select(ptr noalias nocapture readonly %blk1, ptr noali
; CHECK-NEXT: [[J_046:%.*]] = phi i32 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[IF_END_86]] ]
; CHECK-NEXT: [[P2_045:%.*]] = phi ptr [ [[BLK2:%.*]], [[FOR_BODY_LR_PH]] ], [ [[ADD_PTR88:%.*]], [[IF_END_86]] ]
; CHECK-NEXT: [[P1_044:%.*]] = phi ptr [ [[BLK1:%.*]], [[FOR_BODY_LR_PH]] ], [ [[ADD_PTR:%.*]], [[IF_END_86]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr [[P1_044]], align 1
-; CHECK-NEXT: [[TMP1:%.*]] = zext <8 x i8> [[TMP0]] to <8 x i32>
-; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[P2_045]], align 1
-; CHECK-NEXT: [[TMP3:%.*]] = zext <8 x i8> [[TMP2]] to <8 x i32>
-; CHECK-NEXT: [[TMP4:%.*]] = sub nsw <8 x i32> [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = icmp slt <8 x i32> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = sub nsw <8 x i32> zeroinitializer, [[TMP4]]
-; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP5]], <8 x i32> [[TMP6]], <8 x i32> [[TMP4]]
-; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP7]])
-; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP8]], [[S_047]]
+; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[P1_044]], align 1
+; CHECK-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[TMP1]] to <8 x i32>
+; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i8>, ptr [[P2_045]], align 1
+; CHECK-NEXT: [[TMP5:%.*]] = zext <8 x i8> [[TMP4]] to <8 x i32>
+; CHECK-NEXT: [[TMP6:%.*]] = sub nsw <8 x i32> [[TMP2]], [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = icmp slt <8 x i32> [[TMP6]], zeroinitializer
+; CHECK-NEXT: [[TMP8:%.*]] = sub nsw <8 x i32> zeroinitializer, [[TMP6]]
+; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[TMP7]], <8 x i32> [[TMP8]], <8 x i32> [[TMP6]]
+; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP9]])
+; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP10]], [[S_047]]
; CHECK-NEXT: [[CMP83:%.*]] = icmp slt i32 [[OP_RDX]], [[LIM:%.*]]
; CHECK-NEXT: br i1 [[CMP83]], label [[IF_END_86]], label [[FOR_END_LOOPEXIT:%.*]]
; CHECK: if.end.86:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll b/llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
index 4565d4928ba4ad..4132fbaa5c755f 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
@@ -9,17 +9,17 @@ define { i64, i64 } @patatino(double %arg) {
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr @global, align 16
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr getelementptr inbounds ([6 x double], ptr @global, i64 0, i64 2), align 16
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[ARG:%.*]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[TMP0]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = load <2 x double>, ptr getelementptr inbounds ([6 x double], ptr @global, i64 0, i64 4), align 16
-; CHECK-NEXT: [[TMP7:%.*]] = fadd <2 x double> [[TMP6]], [[TMP5]]
-; CHECK-NEXT: [[TMP8:%.*]] = fptosi <2 x double> [[TMP7]] to <2 x i32>
-; CHECK-NEXT: [[TMP9:%.*]] = sext <2 x i32> [[TMP8]] to <2 x i64>
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP9]], i32 0
-; CHECK-NEXT: [[T16:%.*]] = insertvalue { i64, i64 } undef, i64 [[TMP10]], 0
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i64> [[TMP9]], i32 1
-; CHECK-NEXT: [[T17:%.*]] = insertvalue { i64, i64 } [[T16]], i64 [[TMP11]], 1
+; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> [[TMP1]], [[SHUFFLE]]
+; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP0]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([6 x double], ptr @global, i64 0, i64 4), align 16
+; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x double> [[TMP5]], [[TMP4]]
+; CHECK-NEXT: [[TMP7:%.*]] = fptosi <2 x double> [[TMP6]] to <2 x i32>
+; CHECK-NEXT: [[TMP8:%.*]] = sext <2 x i32> [[TMP7]] to <2 x i64>
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP8]], i32 0
+; CHECK-NEXT: [[T16:%.*]] = insertvalue { i64, i64 } undef, i64 [[TMP9]], 0
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP8]], i32 1
+; CHECK-NEXT: [[T17:%.*]] = insertvalue { i64, i64 } [[T16]], i64 [[TMP10]], 1
; CHECK-NEXT: ret { i64, i64 } [[T17]]
;
bb:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll b/llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll
index 651631de2c35ad..903adc8893f346 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll
@@ -20,13 +20,13 @@ define i8 @PR31243_zext(i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %ptr) {
; SSE-NEXT: [[TMP0:%.*]] = or i8 [[V0:%.*]], 1
; SSE-NEXT: [[TMP1:%.*]] = or i8 [[V1:%.*]], 1
; SSE-NEXT: [[TMP2:%.*]] = zext i8 [[TMP0]] to i64
-; SSE-NEXT: [[T4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP2]]
+; SSE-NEXT: [[TMP_4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP2]]
; SSE-NEXT: [[TMP3:%.*]] = zext i8 [[TMP1]] to i64
-; SSE-NEXT: [[T5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP3]]
-; SSE-NEXT: [[T6:%.*]] = load i8, ptr [[T4]], align 1
-; SSE-NEXT: [[T7:%.*]] = load i8, ptr [[T5]], align 1
-; SSE-NEXT: [[T8:%.*]] = add i8 [[T6]], [[T7]]
-; SSE-NEXT: ret i8 [[T8]]
+; SSE-NEXT: [[TMP_5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP3]]
+; SSE-NEXT: [[TMP_6:%.*]] = load i8, ptr [[TMP_4]], align 1
+; SSE-NEXT: [[TMP_7:%.*]] = load i8, ptr [[TMP_5]], align 1
+; SSE-NEXT: [[TMP_8:%.*]] = add i8 [[TMP_6]], [[TMP_7]]
+; SSE-NEXT: ret i8 [[TMP_8]]
;
; AVX-LABEL: @PR31243_zext(
; AVX-NEXT: entry:
@@ -35,26 +35,26 @@ define i8 @PR31243_zext(i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %ptr) {
; AVX-NEXT: [[TMP2:%.*]] = or <2 x i8> [[TMP1]], <i8 1, i8 1>
; AVX-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i64 0
; AVX-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64
-; AVX-NEXT: [[T4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP4]]
+; AVX-NEXT: [[TMP_4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP4]]
; AVX-NEXT: [[TMP5:%.*]] = extractelement <2 x i8> [[TMP2]], i64 1
; AVX-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i64
-; AVX-NEXT: [[T5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP6]]
-; AVX-NEXT: [[T6:%.*]] = load i8, ptr [[T4]], align 1
-; AVX-NEXT: [[T7:%.*]] = load i8, ptr [[T5]], align 1
-; AVX-NEXT: [[T8:%.*]] = add i8 [[T6]], [[T7]]
-; AVX-NEXT: ret i8 [[T8]]
+; AVX-NEXT: [[TMP_5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP6]]
+; AVX-NEXT: [[TMP_6:%.*]] = load i8, ptr [[TMP_4]], align 1
+; AVX-NEXT: [[TMP_7:%.*]] = load i8, ptr [[TMP_5]], align 1
+; AVX-NEXT: [[TMP_8:%.*]] = add i8 [[TMP_6]], [[TMP_7]]
+; AVX-NEXT: ret i8 [[TMP_8]]
;
entry:
- %t0 = zext i8 %v0 to i32
- %t1 = zext i8 %v1 to i32
- %t2 = or i32 %t0, 1
- %t3 = or i32 %t1, 1
- %t4 = getelementptr inbounds i8, ptr %ptr, i32 %t2
- %t5 = getelementptr inbounds i8, ptr %ptr, i32 %t3
- %t6 = load i8, ptr %t4
- %t7 = load i8, ptr %t5
- %t8 = add i8 %t6, %t7
- ret i8 %t8
+ %tmp_0 = zext i8 %v0 to i32
+ %tmp_1 = zext i8 %v1 to i32
+ %tmp_2 = or i32 %tmp_0, 1
+ %tmp_3 = or i32 %tmp_1, 1
+ %tmp_4 = getelementptr inbounds i8, ptr %ptr, i32 %tmp_2
+ %tmp_5 = getelementptr inbounds i8, ptr %ptr, i32 %tmp_3
+ %tmp_6 = load i8, ptr %tmp_4
+ %tmp_7 = load i8, ptr %tmp_5
+ %tmp_8 = add i8 %tmp_6, %tmp_7
+ ret i8 %tmp_8
}
; When computing minimum sizes, if we cannot prove the sign bit is zero, we
@@ -76,13 +76,13 @@ define i8 @PR31243_sext(i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %ptr) {
; SSE-NEXT: [[TMP0:%.*]] = or i8 [[V0:%.*]], 1
; SSE-NEXT: [[TMP1:%.*]] = or i8 [[V1:%.*]], 1
; SSE-NEXT: [[TMP2:%.*]] = sext i8 [[TMP0]] to i64
-; SSE-NEXT: [[T4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP2]]
+; SSE-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP2]]
; SSE-NEXT: [[TMP3:%.*]] = sext i8 [[TMP1]] to i64
-; SSE-NEXT: [[T5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP3]]
-; SSE-NEXT: [[T6:%.*]] = load i8, ptr [[T4]], align 1
-; SSE-NEXT: [[T7:%.*]] = load i8, ptr [[T5]], align 1
-; SSE-NEXT: [[T8:%.*]] = add i8 [[T6]], [[T7]]
-; SSE-NEXT: ret i8 [[T8]]
+; SSE-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP3]]
+; SSE-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP4]], align 1
+; SSE-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP5]], align 1
+; SSE-NEXT: [[TMP8:%.*]] = add i8 [[TMP6]], [[TMP7]]
+; SSE-NEXT: ret i8 [[TMP8]]
;
; AVX-LABEL: @PR31243_sext(
; AVX-NEXT: entry:
@@ -92,24 +92,24 @@ define i8 @PR31243_sext(i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %ptr) {
; AVX-NEXT: [[TMP3:%.*]] = sext <2 x i8> [[TMP2]] to <2 x i16>
; AVX-NEXT: [[TMP4:%.*]] = extractelement <2 x i16> [[TMP3]], i64 0
; AVX-NEXT: [[TMP5:%.*]] = sext i16 [[TMP4]] to i64
-; AVX-NEXT: [[T4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP5]]
+; AVX-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP5]]
; AVX-NEXT: [[TMP6:%.*]] = extractelement <2 x i16> [[TMP3]], i64 1
; AVX-NEXT: [[TMP7:%.*]] = sext i16 [[TMP6]] to i64
-; AVX-NEXT: [[T5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP7]]
-; AVX-NEXT: [[T6:%.*]] = load i8, ptr [[T4]], align 1
-; AVX-NEXT: [[T7:%.*]] = load i8, ptr [[T5]], align 1
-; AVX-NEXT: [[T8:%.*]] = add i8 [[T6]], [[T7]]
-; AVX-NEXT: ret i8 [[T8]]
+; AVX-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP7]]
+; AVX-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP4]], align 1
+; AVX-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP5]], align 1
+; AVX-NEXT: [[TMP8:%.*]] = add i8 [[TMP6]], [[TMP7]]
+; AVX-NEXT: ret i8 [[TMP8]]
;
entry:
- %t0 = sext i8 %v0 to i32
- %t1 = sext i8 %v1 to i32
- %t2 = or i32 %t0, 1
- %t3 = or i32 %t1, 1
- %t4 = getelementptr inbounds i8, ptr %ptr, i32 %t2
- %t5 = getelementptr inbounds i8, ptr %ptr, i32 %t3
- %t6 = load i8, ptr %t4
- %t7 = load i8, ptr %t5
- %t8 = add i8 %t6, %t7
- ret i8 %t8
+ %tmp0 = sext i8 %v0 to i32
+ %tmp1 = sext i8 %v1 to i32
+ %tmp2 = or i32 %tmp0, 1
+ %tmp3 = or i32 %tmp1, 1
+ %tmp4 = getelementptr inbounds i8, ptr %ptr, i32 %tmp2
+ %tmp5 = getelementptr inbounds i8, ptr %ptr, i32 %tmp3
+ %tmp6 = load i8, ptr %tmp4
+ %tmp7 = load i8, ptr %tmp5
+ %tmp8 = add i8 %tmp6, %tmp7
+ ret i8 %tmp8
}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/multi-node-with-save-values.ll b/llvm/test/Transforms/SLPVectorizer/X86/multi-node-with-save-values.ll
index 1a129f6ed80505..2088a3db212bed 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/multi-node-with-save-values.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/multi-node-with-save-values.ll
@@ -7,9 +7,9 @@ define void @foo() {
; CHECK-NEXT: br label [[BB1:%.*]]
; CHECK: bb1:
; CHECK-NEXT: switch i32 0, label [[BB3:%.*]] [
-; CHECK-NEXT: i32 0, label [[BB2:%.*]]
-; CHECK-NEXT: i32 4, label [[BB4:%.*]]
-; CHECK-NEXT: i32 1, label [[BB4]]
+; CHECK-NEXT: i32 0, label [[BB2:%.*]]
+; CHECK-NEXT: i32 4, label [[BB4:%.*]]
+; CHECK-NEXT: i32 1, label [[BB4]]
; CHECK-NEXT: ]
; CHECK: bb2:
; CHECK-NEXT: br label [[BB4]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vectorize-cmps.ll b/llvm/test/Transforms/SLPVectorizer/X86/vectorize-cmps.ll
index b8a2d8431b1e6b..b2e0af3b58ce53 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vectorize-cmps.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vectorize-cmps.ll
@@ -4,13 +4,13 @@
define i32 @test(ptr %isec, float %0) {
; CHECK-LABEL: @test(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[ISEC:%.*]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[TMP0:%.*]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <2 x float> [[TMP2]], [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[ISEC:%.*]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[TMP0:%.*]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = fmul fast <2 x float> [[TMP3]], [[TMP2]]
; CHECK-NEXT: [[CMP61:%.*]] = fcmp fast oge float 0.000000e+00, 0.000000e+00
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP3]], i32 1
-; CHECK-NEXT: [[CMP63:%.*]] = fcmp fast ogt float [[TMP4]], [[TMP5]]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x float> [[TMP4]], i32 1
+; CHECK-NEXT: [[CMP63:%.*]] = fcmp fast ogt float [[TMP5]], [[TMP6]]
; CHECK-NEXT: br i1 [[CMP63]], label [[CLEANUP:%.*]], label [[IF_END:%.*]]
; CHECK: if.end:
; CHECK-NEXT: br label [[CLEANUP]]
diff --git a/llvm/test/Transforms/SROA/tbaa-struct2.ll b/llvm/test/Transforms/SROA/tbaa-struct2.ll
index 02c99a2b329457..1fd37e82d67775 100644
--- a/llvm/test/Transforms/SROA/tbaa-struct2.ll
+++ b/llvm/test/Transforms/SROA/tbaa-struct2.ll
@@ -13,9 +13,9 @@ define double @bar(ptr %wishart) {
; CHECK-NEXT: [[TMP_SROA_3:%.*]] = alloca [4 x i8], align 4
; CHECK-NEXT: [[TMP_SROA_0_0_COPYLOAD:%.*]] = load double, ptr [[WISHART:%.*]], align 8, !tbaa.struct [[TBAA_STRUCT0:![0-9]+]]
; CHECK-NEXT: [[TMP_SROA_2_0_WISHART_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[WISHART]], i64 8
-; CHECK-NEXT: [[TMP_SROA_2_0_COPYLOAD:%.*]] = load i32, ptr [[TMP_SROA_2_0_WISHART_SROA_IDX]], align 8, !tbaa [[TBAA5:![0-9]+]]
+; CHECK-NEXT: [[TMP_SROA_2_0_COPYLOAD:%.*]] = load i32, ptr [[TMP_SROA_2_0_WISHART_SROA_IDX]], align 8, !tbaa.struct [[TBAA_STRUCT7:![0-9]+]]
; CHECK-NEXT: [[TMP_SROA_3_0_WISHART_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[WISHART]], i64 12
-; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP_SROA_3]], ptr align 4 [[TMP_SROA_3_0_WISHART_SROA_IDX]], i64 4, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]]
+; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP_SROA_3]], ptr align 4 [[TMP_SROA_3_0_WISHART_SROA_IDX]], i64 4, i1 false), !tbaa.struct [[TBAA_STRUCT8:![0-9]+]]
; CHECK-NEXT: [[CALL:%.*]] = call double @subcall(double [[TMP_SROA_0_0_COPYLOAD]], i32 [[TMP_SROA_2_0_COPYLOAD]])
; CHECK-NEXT: ret double [[CALL]]
;
@@ -38,14 +38,15 @@ define double @bar(ptr %wishart) {
;.
; CHECK: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
;.
-; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 8, [[META1:![0-9]+]], i64 8, i64 4, [[TBAA5]]}
-; CHECK: [[META1]] = !{[[META2:![0-9]+]], [[META2]], i64 0}
-; CHECK: [[META2]] = !{!"double", [[META3:![0-9]+]], i64 0}
-; CHECK: [[META3]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0}
-; CHECK: [[META4]] = !{!"Simple C++ TBAA"}
-; CHECK: [[TBAA5]] = !{[[META6:![0-9]+]], [[META6]], i64 0}
-; CHECK: [[META6]] = !{!"int", [[META3]], i64 0}
-; CHECK: [[TBAA_STRUCT7]] = !{}
+; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 8, !1, i64 8, i64 4, !5}
+; CHECK: [[META1:![0-9]+]] = !{!2, !2, i64 0}
+; CHECK: [[META2:![0-9]+]] = !{!"double", !3, i64 0}
+; CHECK: [[META3:![0-9]+]] = !{!"omnipotent char", !4, i64 0}
+; CHECK: [[META4:![0-9]+]] = !{!"Simple C++ TBAA"}
+; CHECK: [[META5:![0-9]+]] = !{!6, !6, i64 0}
+; CHECK: [[META6:![0-9]+]] = !{!"int", !3, i64 0}
+; CHECK: [[TBAA_STRUCT7]] = !{i64 0, i64 4, !5}
+; CHECK: [[TBAA_STRUCT8]] = !{}
;.
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-MODIFY-CFG: {{.*}}
diff --git a/llvm/test/Transforms/SROA/tbaa-struct3.ll b/llvm/test/Transforms/SROA/tbaa-struct3.ll
index 2a151c01adfcc0..71a4a126710aa2 100644
--- a/llvm/test/Transforms/SROA/tbaa-struct3.ll
+++ b/llvm/test/Transforms/SROA/tbaa-struct3.ll
@@ -10,9 +10,9 @@ define void @load_store_transfer_split_struct_tbaa_2_float(ptr dereferenceable(2
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[A]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[B]] to i32
-; CHECK-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4, !tbaa.struct [[TBAA_STRUCT0:![0-9]+]]
+; CHECK-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4
; CHECK-NEXT: [[RES_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[RES]], i64 4
-; CHECK-NEXT: store i32 [[TMP1]], ptr [[RES_SROA_IDX]], align 4, !tbaa [[TBAA1:![0-9]+]]
+; CHECK-NEXT: store i32 [[TMP1]], ptr [[RES_SROA_IDX]], align 4
; CHECK-NEXT: [[P:%.*]] = load ptr, ptr [[RES]], align 8
; CHECK-NEXT: ret void
;
@@ -32,9 +32,9 @@ define void @memcpy_transfer(ptr dereferenceable(24) %res, float %a, float %b) {
; CHECK-SAME: ptr dereferenceable(24) [[RES:%.*]], float [[A:%.*]], float [[B:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[L_PTR:%.*]] = load ptr, ptr [[RES]], align 8
-; CHECK-NEXT: store float [[A]], ptr [[L_PTR]], align 1, !tbaa.struct [[TBAA_STRUCT0]]
+; CHECK-NEXT: store float [[A]], ptr [[L_PTR]], align 1, !tbaa.struct [[TBAA_STRUCT0:![0-9]+]]
; CHECK-NEXT: [[TMP_SROA_2_0_L_PTR_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[L_PTR]], i64 4
-; CHECK-NEXT: store float [[B]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa [[TBAA1]]
+; CHECK-NEXT: store float [[B]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa.struct [[TBAA_STRUCT5:![0-9]+]]
; CHECK-NEXT: ret void
;
entry:
@@ -56,7 +56,7 @@ define void @memcpy_transfer_tbaa_field_and_size_do_not_align(ptr dereferenceabl
; CHECK-NEXT: [[TMP_SROA_2_0_L_PTR_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[L_PTR]], i64 4
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[B]] to i32
; CHECK-NEXT: [[TMP_SROA_2_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[TMP0]] to i16
-; CHECK-NEXT: store i16 [[TMP_SROA_2_0_EXTRACT_TRUNC]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa.struct [[TBAA_STRUCT5:![0-9]+]]
+; CHECK-NEXT: store i16 [[TMP_SROA_2_0_EXTRACT_TRUNC]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa.struct [[TBAA_STRUCT5]]
; CHECK-NEXT: ret void
;
entry:
@@ -100,7 +100,7 @@ define void @store_vector_part_first(ptr %y2, float %f) {
; CHECK-NEXT: [[V_1:%.*]] = call <2 x float> @foo(ptr [[Y2]])
; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[Y2]], align 8, !tbaa.struct [[TBAA_STRUCT6:![0-9]+]]
; CHECK-NEXT: [[X7_SROA_2_0_Y2_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[Y2]], i64 8
-; CHECK-NEXT: store float [[F]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 8, !tbaa [[TBAA1]]
+; CHECK-NEXT: store float [[F]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 8, !tbaa.struct [[TBAA_STRUCT5]]
; CHECK-NEXT: ret void
;
%x7 = alloca { float, float, float, float }
@@ -118,7 +118,7 @@ define void @store_vector_part_second(ptr %y2, float %f) {
; CHECK-NEXT: [[V_1:%.*]] = call <2 x float> @foo(ptr [[Y2]])
; CHECK-NEXT: store float [[F]], ptr [[Y2]], align 8, !tbaa.struct [[TBAA_STRUCT9:![0-9]+]]
; CHECK-NEXT: [[X7_SROA_2_0_Y2_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[Y2]], i64 4
-; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 4, !tbaa [[TBAA7:![0-9]+]]
+; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 4, !tbaa.struct [[TBAA_STRUCT10:![0-9]+]]
; CHECK-NEXT: ret void
;
%x7 = alloca { float, float, float, float }
@@ -134,7 +134,7 @@ define void @store_vector_single(ptr %y2, float %f) {
; CHECK-LABEL: define void @store_vector_single(
; CHECK-SAME: ptr [[Y2:%.*]], float [[F:%.*]]) {
; CHECK-NEXT: [[V_1:%.*]] = call <2 x float> @foo(ptr [[Y2]])
-; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[Y2]], align 4, !tbaa.struct [[TBAA_STRUCT10:![0-9]+]]
+; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[Y2]], align 4, !tbaa.struct [[TBAA_STRUCT11:![0-9]+]]
; CHECK-NEXT: ret void
;
%x7 = alloca { float, float }
@@ -161,8 +161,8 @@ define void @memset(ptr %dst, ptr align 8 %src) {
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[A_SROA_4]], ptr align 1 [[A_SROA_4_0_SRC_SROA_IDX]], i32 10, i1 false)
; CHECK-NEXT: store i16 1, ptr [[A_SROA_3]], align 2
; CHECK-NEXT: [[A_SROA_0_1_A_1_SROA_IDX2:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_0]], i64 1
-; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_1_A_1_SROA_IDX2]], i8 42, i32 6, i1 false), !tbaa.struct [[TBAA_STRUCT11:![0-9]+]]
-; CHECK-NEXT: store i16 10794, ptr [[A_SROA_3]], align 2, !tbaa [[TBAA1]]
+; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_1_A_1_SROA_IDX2]], i8 42, i32 6, i1 false), !tbaa.struct [[TBAA_STRUCT12:![0-9]+]]
+; CHECK-NEXT: store i16 10794, ptr [[A_SROA_3]], align 2, !tbaa.struct [[TBAA_STRUCT13:![0-9]+]]
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 1 [[A_SROA_0]], i32 7, i1 true)
; CHECK-NEXT: [[A_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 7
; CHECK-NEXT: [[A_SROA_3_0_A_SROA_3_0_COPYLOAD1:%.*]] = load volatile i16, ptr [[A_SROA_3]], align 2
@@ -199,8 +199,8 @@ define void @memset2(ptr %dst, ptr align 8 %src) {
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[A_SROA_4]], ptr align 2 [[A_SROA_4_0_SRC_SROA_IDX]], i32 90, i1 false)
; CHECK-NEXT: store i8 1, ptr [[A_SROA_3]], align 1
; CHECK-NEXT: [[A_SROA_0_202_A_202_SROA_IDX2:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_0]], i64 202
-; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_202_A_202_SROA_IDX2]], i8 42, i32 7, i1 false), !tbaa.struct [[TBAA_STRUCT12:![0-9]+]]
-; CHECK-NEXT: store i8 42, ptr [[A_SROA_3]], align 1, !tbaa [[TBAA7]]
+; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_202_A_202_SROA_IDX2]], i8 42, i32 7, i1 false), !tbaa.struct [[TBAA_STRUCT14:![0-9]+]]
+; CHECK-NEXT: store i8 42, ptr [[A_SROA_3]], align 1, !tbaa.struct [[TBAA_STRUCT15:![0-9]+]]
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 1 [[A_SROA_0]], i32 209, i1 true)
; CHECK-NEXT: [[A_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 209
; CHECK-NEXT: [[A_SROA_3_0_A_SROA_3_0_COPYLOAD1:%.*]] = load volatile i8, ptr [[A_SROA_3]], align 1
@@ -240,7 +240,7 @@ define void @slice_store_v2i8_1(ptr %dst, ptr %dst.2, ptr %src) {
; CHECK-NEXT: [[A_SROA_2_0_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 6
; CHECK-NEXT: [[A_SROA_2_SROA_0_0_COPYLOAD:%.*]] = load <2 x i8>, ptr [[A_SROA_2_0_SRC_SROA_IDX]], align 2
; CHECK-NEXT: store <2 x i8> [[A_SROA_2_SROA_0_0_COPYLOAD]], ptr [[A_SROA_2_SROA_0]], align 4
-; CHECK-NEXT: store <2 x i8> bitcast (<1 x i16> <i16 123> to <2 x i8>), ptr [[A_SROA_2_SROA_0]], align 4, !tbaa.struct [[TBAA_STRUCT13:![0-9]+]]
+; CHECK-NEXT: store <2 x i8> bitcast (<1 x i16> <i16 123> to <2 x i8>), ptr [[A_SROA_2_SROA_0]], align 4, !tbaa.struct [[TBAA_STRUCT16:![0-9]+]]
; CHECK-NEXT: [[A_SROA_2_SROA_0_0_A_SROA_2_SROA_0_0_A_SROA_2_6_V_4:%.*]] = load <2 x i8>, ptr [[A_SROA_2_SROA_0]], align 4
; CHECK-NEXT: store <2 x i8> [[A_SROA_2_SROA_0_0_A_SROA_2_SROA_0_0_A_SROA_2_6_V_4]], ptr [[DST_2]], align 2
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 1 [[A_SROA_0]], i32 6, i1 true)
@@ -279,8 +279,8 @@ define void @slice_store_v2i8_2(ptr %dst, ptr %dst.2, ptr %src) {
; CHECK-NEXT: store i8 [[A_SROA_0_SROA_4_1_COPYLOAD]], ptr [[A_SROA_0_SROA_4]], align 1
; CHECK-NEXT: [[A_SROA_4_1_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 3
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[A_SROA_4]], ptr align 1 [[A_SROA_4_1_SRC_SROA_IDX]], i32 5, i1 false)
-; CHECK-NEXT: store <2 x i8> zeroinitializer, ptr [[A_SROA_0_SROA_1]], align 2, !tbaa.struct [[TBAA_STRUCT14:![0-9]+]]
-; CHECK-NEXT: store i8 0, ptr [[A_SROA_0_SROA_4]], align 1, !tbaa [[TBAA1]]
+; CHECK-NEXT: store <2 x i8> zeroinitializer, ptr [[A_SROA_0_SROA_1]], align 2, !tbaa.struct [[TBAA_STRUCT17:![0-9]+]]
+; CHECK-NEXT: store i8 0, ptr [[A_SROA_0_SROA_4]], align 1, !tbaa.struct [[TBAA_STRUCT18:![0-9]+]]
; CHECK-NEXT: [[A_SROA_0_SROA_1_0_A_SROA_0_SROA_1_1_A_SROA_0_1_V_4:%.*]] = load <2 x i8>, ptr [[A_SROA_0_SROA_1]], align 2
; CHECK-NEXT: store <2 x i8> [[A_SROA_0_SROA_1_0_A_SROA_0_SROA_1_1_A_SROA_0_1_V_4]], ptr [[DST_2]], align 2
; CHECK-NEXT: [[A_SROA_0_SROA_1_0_A_SROA_0_SROA_1_1_COPYLOAD3:%.*]] = load volatile <2 x i8>, ptr [[A_SROA_0_SROA_1]], align 2
@@ -317,7 +317,7 @@ define double @tbaa_struct_load(ptr %src, ptr %dst) {
; CHECK-NEXT: [[TMP_SROA_3_0_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 8
; CHECK-NEXT: [[TMP_SROA_3_0_COPYLOAD:%.*]] = load i64, ptr [[TMP_SROA_3_0_SRC_SROA_IDX]], align 8
; CHECK-NEXT: store i64 [[TMP_SROA_3_0_COPYLOAD]], ptr [[TMP_SROA_3]], align 8
-; CHECK-NEXT: [[TMP_SROA_0_0_TMP_SROA_0_0_LG:%.*]] = load double, ptr [[TMP_SROA_0]], align 8, !tbaa [[TBAA7]]
+; CHECK-NEXT: [[TMP_SROA_0_0_TMP_SROA_0_0_LG:%.*]] = load double, ptr [[TMP_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT10]]
; CHECK-NEXT: [[TMP_SROA_0_0_TMP_SROA_0_0_COPYLOAD1:%.*]] = load volatile double, ptr [[TMP_SROA_0]], align 8
; CHECK-NEXT: store volatile double [[TMP_SROA_0_0_TMP_SROA_0_0_COPYLOAD1]], ptr [[DST]], align 8
; CHECK-NEXT: [[TMP_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 8
@@ -356,7 +356,7 @@ define i32 @shorten_integer_store_multiple_fields(ptr %dst, ptr %dst.2, ptr %src
; CHECK-SAME: ptr [[DST:%.*]], ptr [[DST_2:%.*]], ptr [[SRC:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca i32, align 4
-; CHECK-NEXT: store i32 123, ptr [[A_SROA_0]], align 4, !tbaa [[TBAA7]]
+; CHECK-NEXT: store i32 123, ptr [[A_SROA_0]], align 4, !tbaa.struct [[TBAA_STRUCT19:![0-9]+]]
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_L:%.*]] = load i32, ptr [[A_SROA_0]], align 4
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_COPYLOAD:%.*]] = load volatile i32, ptr [[A_SROA_0]], align 4
; CHECK-NEXT: store volatile i32 [[A_SROA_0_0_A_SROA_0_0_COPYLOAD]], ptr [[DST]], align 1
@@ -393,7 +393,7 @@ define <2 x i16> @shorten_vector_store_single_fields(ptr %dst, ptr %dst.2, ptr %
; CHECK-SAME: ptr [[DST:%.*]], ptr [[DST_2:%.*]], ptr [[SRC:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca <2 x i32>, align 8
-; CHECK-NEXT: store <2 x i32> <i32 1, i32 2>, ptr [[A_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT15:![0-9]+]]
+; CHECK-NEXT: store <2 x i32> <i32 1, i32 2>, ptr [[A_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT19]]
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_L:%.*]] = load <2 x i16>, ptr [[A_SROA_0]], align 8
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 8 [[A_SROA_0]], i32 4, i1 true)
; CHECK-NEXT: ret <2 x i16> [[A_SROA_0_0_A_SROA_0_0_L]]
@@ -429,11 +429,11 @@ define i32 @split_load_with_tbaa_struct(i32 %x, ptr %src, ptr %dst) {
; CHECK-NEXT: [[A3_SROA_5_0_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 9
; CHECK-NEXT: [[A3_SROA_5_0_COPYLOAD:%.*]] = load i8, ptr [[A3_SROA_5_0_SRC_SROA_IDX]], align 1
; CHECK-NEXT: store i8 [[A3_SROA_5_0_COPYLOAD]], ptr [[A3_SROA_5]], align 1
-; CHECK-NEXT: [[A3_SROA_0_0_A3_SROA_0_0_LOAD4_FCA_0_LOAD:%.*]] = load i16, ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT16:![0-9]+]]
+; CHECK-NEXT: [[A3_SROA_0_0_A3_SROA_0_0_LOAD4_FCA_0_LOAD:%.*]] = load i16, ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT20:![0-9]+]]
; CHECK-NEXT: [[LOAD4_FCA_0_INSERT:%.*]] = insertvalue { i16, float, i8 } poison, i16 [[A3_SROA_0_0_A3_SROA_0_0_LOAD4_FCA_0_LOAD]], 0
-; CHECK-NEXT: [[A3_SROA_33_0_A3_SROA_33_4_LOAD4_FCA_1_LOAD:%.*]] = load float, ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT17:![0-9]+]]
+; CHECK-NEXT: [[A3_SROA_33_0_A3_SROA_33_4_LOAD4_FCA_1_LOAD:%.*]] = load float, ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT21:![0-9]+]]
; CHECK-NEXT: [[LOAD4_FCA_1_INSERT:%.*]] = insertvalue { i16, float, i8 } [[LOAD4_FCA_0_INSERT]], float [[A3_SROA_33_0_A3_SROA_33_4_LOAD4_FCA_1_LOAD]], 1
-; CHECK-NEXT: [[A3_SROA_4_0_A3_SROA_4_8_LOAD4_FCA_2_LOAD:%.*]] = load i8, ptr [[A3_SROA_4]], align 8, !tbaa [[TBAA7]]
+; CHECK-NEXT: [[A3_SROA_4_0_A3_SROA_4_8_LOAD4_FCA_2_LOAD:%.*]] = load i8, ptr [[A3_SROA_4]], align 8, !tbaa.struct [[TBAA_STRUCT15]]
; CHECK-NEXT: [[LOAD4_FCA_2_INSERT:%.*]] = insertvalue { i16, float, i8 } [[LOAD4_FCA_1_INSERT]], i8 [[A3_SROA_4_0_A3_SROA_4_8_LOAD4_FCA_2_LOAD]], 2
; CHECK-NEXT: [[UNWRAP2:%.*]] = extractvalue { i16, float, i8 } [[LOAD4_FCA_2_INSERT]], 1
; CHECK-NEXT: [[VALCAST2:%.*]] = bitcast float [[UNWRAP2]] to i32
@@ -492,11 +492,11 @@ define i32 @split_store_with_tbaa_struct(i32 %x, ptr %src, ptr %dst) {
; CHECK-NEXT: [[I_2:%.*]] = insertvalue { i16, float, i8 } [[I_1]], float 3.000000e+00, 1
; CHECK-NEXT: [[I_3:%.*]] = insertvalue { i16, float, i8 } [[I_2]], i8 99, 2
; CHECK-NEXT: [[I_3_FCA_0_EXTRACT:%.*]] = extractvalue { i16, float, i8 } [[I_3]], 0
-; CHECK-NEXT: store i16 [[I_3_FCA_0_EXTRACT]], ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT16]]
+; CHECK-NEXT: store i16 [[I_3_FCA_0_EXTRACT]], ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT20]]
; CHECK-NEXT: [[I_3_FCA_1_EXTRACT:%.*]] = extractvalue { i16, float, i8 } [[I_3]], 1
-; CHECK-NEXT: store float [[I_3_FCA_1_EXTRACT]], ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT17]]
+; CHECK-NEXT: store float [[I_3_FCA_1_EXTRACT]], ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT21]]
; CHECK-NEXT: [[I_3_FCA_2_EXTRACT:%.*]] = extractvalue { i16, float, i8 } [[I_3]], 2
-; CHECK-NEXT: store i8 [[I_3_FCA_2_EXTRACT]], ptr [[A3_SROA_4]], align 8, !tbaa [[TBAA7]]
+; CHECK-NEXT: store i8 [[I_3_FCA_2_EXTRACT]], ptr [[A3_SROA_4]], align 8, !tbaa.struct [[TBAA_STRUCT15]]
; CHECK-NEXT: [[A3_SROA_0_0_A3_SROA_0_0_COPYLOAD1:%.*]] = load volatile i16, ptr [[A3_SROA_0]], align 8
; CHECK-NEXT: store volatile i16 [[A3_SROA_0_0_A3_SROA_0_0_COPYLOAD1]], ptr [[DST]], align 1
; CHECK-NEXT: [[A3_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 2
@@ -548,22 +548,26 @@ declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias
!15 = !{i64 0, i64 7, !6, i64 7, i64 1, !6}
!16 = !{i64 0, i64 2, !6, i64 4, i64 4, !6, i64 8, i64 1, !6}
;.
-; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 4, [[TBAA1]], i64 4, i64 4, [[TBAA1]]}
-; CHECK: [[TBAA1]] = !{[[META2:![0-9]+]], [[META2]], i64 0}
+; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 4, [[META1:![0-9]+]], i64 4, i64 4, [[META1]]}
+; CHECK: [[META1]] = !{[[META2:![0-9]+]], [[META2]], i64 0}
; CHECK: [[META2]] = !{!"float", [[META3:![0-9]+]], i64 0}
; CHECK: [[META3]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0}
; CHECK: [[META4]] = !{!"Simple C++ TBAA"}
-; CHECK: [[TBAA_STRUCT5]] = !{i64 0, i64 4, [[TBAA1]]}
-; CHECK: [[TBAA_STRUCT6]] = !{i64 0, i64 8, [[TBAA7]], i64 8, i64 4, [[TBAA1]]}
-; CHECK: [[TBAA7]] = !{[[META8:![0-9]+]], [[META8]], i64 0}
+; CHECK: [[TBAA_STRUCT5]] = !{i64 0, i64 4, [[META1]]}
+; CHECK: [[TBAA_STRUCT6]] = !{i64 0, i64 8, [[META7:![0-9]+]], i64 8, i64 4, [[META1]]}
+; CHECK: [[META7]] = !{[[META8:![0-9]+]], [[META8]], i64 0}
; CHECK: [[META8]] = !{!"v2f32", [[META3]], i64 0}
-; CHECK: [[TBAA_STRUCT9]] = !{i64 0, i64 4, [[TBAA1]], i64 4, i64 8, [[TBAA7]]}
-; CHECK: [[TBAA_STRUCT10]] = !{i64 0, i64 8, [[TBAA7]], i64 4, i64 8, [[TBAA1]]}
-; CHECK: [[TBAA_STRUCT11]] = !{i64 0, i64 2, [[TBAA1]], i64 2, i64 6, [[TBAA1]]}
-; CHECK: [[TBAA_STRUCT12]] = !{i64 0, i64 7, [[TBAA7]], i64 7, i64 1, [[TBAA7]]}
-; CHECK: [[TBAA_STRUCT13]] = !{i64 0, i64 2, [[TBAA1]], i64 2, i64 2, [[TBAA1]]}
-; CHECK: [[TBAA_STRUCT14]] = !{i64 0, i64 3, [[TBAA1]]}
-; CHECK: [[TBAA_STRUCT15]] = !{i64 0, i64 4, [[TBAA7]]}
-; CHECK: [[TBAA_STRUCT16]] = !{i64 0, i64 2, [[TBAA7]], i64 4, i64 4, [[TBAA7]], i64 8, i64 1, [[TBAA7]]}
-; CHECK: [[TBAA_STRUCT17]] = !{i64 0, i64 4, [[TBAA7]], i64 4, i64 1, [[TBAA7]]}
+; CHECK: [[TBAA_STRUCT9]] = !{i64 0, i64 4, [[META1]], i64 4, i64 8, [[META7]]}
+; CHECK: [[TBAA_STRUCT10]] = !{i64 0, i64 8, [[META7]]}
+; CHECK: [[TBAA_STRUCT11]] = !{i64 0, i64 8, [[META7]], i64 4, i64 8, [[META1]]}
+; CHECK: [[TBAA_STRUCT12]] = !{i64 0, i64 2, [[META1]], i64 2, i64 6, [[META1]]}
+; CHECK: [[TBAA_STRUCT13]] = !{i64 0, i64 2, [[META1]]}
+; CHECK: [[TBAA_STRUCT14]] = !{i64 0, i64 7, [[META7]], i64 7, i64 1, [[META7]]}
+; CHECK: [[TBAA_STRUCT15]] = !{i64 0, i64 1, [[META7]]}
+; CHECK: [[TBAA_STRUCT16]] = !{i64 0, i64 2, [[META1]], i64 2, i64 2, [[META1]]}
+; CHECK: [[TBAA_STRUCT17]] = !{i64 0, i64 3, [[META1]]}
+; CHECK: [[TBAA_STRUCT18]] = !{i64 0, i64 1, [[META1]]}
+; CHECK: [[TBAA_STRUCT19]] = !{i64 0, i64 4, [[META7]]}
+; CHECK: [[TBAA_STRUCT20]] = !{i64 0, i64 2, [[META7]], i64 4, i64 4, [[META7]], i64 8, i64 1, [[META7]]}
+; CHECK: [[TBAA_STRUCT21]] = !{i64 0, i64 4, [[META7]], i64 4, i64 1, [[META7]]}
;.
diff --git a/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test b/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
index f88b7575002a94..fc5856691f8dca 100644
--- a/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
+++ b/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
@@ -48,9 +48,6 @@
# RUN: llvm-objcopy -I binary -O elf64-loongarch %t.txt %t.la64.o
# RUN: llvm-readobj --file-headers %t.la64.o | FileCheck %s --check-prefixes=CHECK,LE,LA64,64
-# RUN: llvm-objcopy -I binary -O elf64-s390 %t.txt %t.s390x.o
-# RUN: llvm-readobj --file-headers %t.s390x.o | FileCheck %s --check-prefixes=CHECK,BE,S390X,64
-
# CHECK: Format:
# 32-SAME: elf32-
# 64-SAME: elf64-
@@ -67,7 +64,6 @@
# PPCLE-SAME: powerpcle{{$}}
# SPARC-SAME: sparc
# SPARCEL-SAME: sparc
-# S390X-SAME: s390
# X86-64-SAME: x86-64
# AARCH64-NEXT: Arch: aarch64
@@ -85,7 +81,6 @@
# RISCV64-NEXT: Arch: riscv64
# SPARC-NEXT: Arch: sparc{{$}}
# SPARCEL-NEXT: Arch: sparcel
-# S390X-NEXT: Arch: s390x
# X86-64-NEXT: Arch: x86_64
# 32-NEXT: AddressSize: 32bit
@@ -121,7 +116,6 @@
# RISCV64-NEXT: Machine: EM_RISCV (0xF3)
# SPARC-NEXT: Machine: EM_SPARC (0x2)
# SPARCEL-NEXT: Machine: EM_SPARC (0x2)
-# S390X-NEXT: Machine: EM_S390 (0x16)
# X86-64-NEXT: Machine: EM_X86_64 (0x3E)
# CHECK-NEXT: Version: 1
diff --git a/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test b/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test
index 9a8128611792d5..882940c05e19c2 100644
--- a/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test
+++ b/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test
@@ -117,10 +117,6 @@
# RUN: llvm-readobj --file-headers %t.elf64_loongarch.o | FileCheck %s --check-prefixes=CHECK,LE,LA64,64,SYSV
# RUN: llvm-readobj --file-headers %t.elf64_loongarch.dwo | FileCheck %s --check-prefixes=CHECK,LE,LA64,64,SYSV
-# RUN: llvm-objcopy %t.o -O elf64-s390 %t.elf64_s390.o --split-dwo=%t.elf64_s390.dwo
-# RUN: llvm-readobj --file-headers %t.elf64_s390.o | FileCheck %s --check-prefixes=CHECK,BE,S390X,64,SYSV
-# RUN: llvm-readobj --file-headers %t.elf64_s390.dwo | FileCheck %s --check-prefixes=CHECK,BE,S390X,64,SYSV
-
!ELF
FileHeader:
Class: ELFCLASS32
@@ -164,7 +160,6 @@ Symbols:
# RISCV32-SAME: riscv{{$}}
# RISCV64-SAME: riscv{{$}}
# SPARC-SAME: sparc
-# S390X-SAME: s390
# X86-64-SAME: x86-64
# DEFAULT-SAME: unknown
@@ -187,7 +182,6 @@ Symbols:
# RISCV64-NEXT: Arch: riscv64
# SPARC-NEXT: Arch: sparc{{$}}
# SPARCEL-NEXT: Arch: sparcel
-# S390X-NEXT: Arch: s390x
# X86-64-NEXT: Arch: x86_64
# DEFAULT-NEXT: Arch: unknown
@@ -216,7 +210,6 @@ Symbols:
# RISCV32: Machine: EM_RISCV (0xF3)
# RISCV64: Machine: EM_RISCV (0xF3)
# SPARC: Machine: EM_SPARC (0x2)
-# S390X: Machine: EM_S390 (0x16)
# X86-64: Machine: EM_X86_64 (0x3E)
# 32: HeaderSize: 52
>From 6138c467bb2f94c672763d84bbf7a928ca132dad Mon Sep 17 00:00:00 2001
From: Alan Zhao <ayzhao at google.com>
Date: Fri, 16 Feb 2024 11:33:06 -0800
Subject: [PATCH 2/2] Undo changes to accidentally modified files
---
.../Analysis/CostModel/RISCV/rvv-shuffle.ll | 4 +-
.../CostModel/RISCV/rvv-vectorextract.ll | 56 +-
.../RISCV/shuffle-extract_subvector.ll | 72 +-
llvm/test/CodeGen/AArch64/arm64-stur.ll | 5 +-
llvm/test/CodeGen/AArch64/merge-store.ll | 3 +-
.../AArch64/storepairsuppress_minsize.ll | 92 +-
.../RISCV/atomic-cmpxchg-branch-on-result.ll | 22 +
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll | 1122 +-
llvm/test/CodeGen/RISCV/atomic-rmw.ll | 14384 +++++++++++-----
llvm/test/Transforms/InstCombine/fsh.ll | 128 +
.../InstCombine/struct-assign-tbaa.ll | 5 +-
.../LoopVectorize/trunc-reductions.ll | 65 +
.../SLPVectorizer/AArch64/horizontal.ll | 46 +-
.../Transforms/SLPVectorizer/X86/PR35777.ll | 22 +-
.../SLPVectorizer/X86/minimum-sizes.ll | 88 +-
.../X86/multi-node-with-save-values.ll | 6 +-
.../SLPVectorizer/X86/vectorize-cmps.ll | 12 +-
llvm/test/Transforms/SROA/tbaa-struct2.ll | 21 +-
llvm/test/Transforms/SROA/tbaa-struct3.ll | 80 +-
.../ELF/binary-output-target.test | 6 +
.../llvm-objcopy/ELF/cross-arch-headers.test | 7 +
21 files changed, 11910 insertions(+), 4336 deletions(-)
diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
index 4f3c7e2f90c655..30da63b3feec65 100644
--- a/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
@@ -52,14 +52,14 @@ define void @vector_broadcast() {
define void @vector_insert_extract(<vscale x 4 x i32> %v0, <vscale x 16 x i32> %v1, <16 x i32> %v2) {
; CHECK-LABEL: 'vector_insert_extract'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %insert_fixed_into_scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> %v0, <16 x i32> %v2, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %extract_scalable_from_scalable = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %v1, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %insert_scalable_into_scalable = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> %v1, <vscale x 4 x i32> %v0, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'vector_insert_extract'
-; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %insert_fixed_into_scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> %v0, <16 x i32> %v2, i64 0)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %extract_scalable_from_scalable = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %v1, i64 0)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %insert_scalable_into_scalable = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> %v1, <vscale x 4 x i32> %v0, i64 0)
diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-vectorextract.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-vectorextract.ll
index 1e2d1f4d94954e..61f80b643cf78d 100644
--- a/llvm/test/Analysis/CostModel/RISCV/rvv-vectorextract.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/rvv-vectorextract.ll
@@ -11,13 +11,13 @@ define void @vector_extract_nxv128i8_0(<vscale x 128 x i8> %v) {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %scalable_m2 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %scalable_m4 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %scalable_m8 = call <vscale x 64 x i8> @llvm.vector.extract.nxv64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'vector_extract_nxv128i8_0'
@@ -28,13 +28,13 @@ define void @vector_extract_nxv128i8_0(<vscale x 128 x i8> %v) {
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %scalable_m2 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %scalable_m4 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %scalable_m8 = call <vscale x 64 x i8> @llvm.vector.extract.nxv64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%scalable_mf8 = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
@@ -110,23 +110,23 @@ define void @vector_extract_nxv128i8_1(<vscale x 128 x i8> %v) {
define void @vector_extract_v128i8_0(<128 x i8> %v) {
; CHECK-LABEL: 'vector_extract_v128i8_0'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.v128i8(<128 x i8> %v, i64 0)
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'vector_extract_v128i8_0'
-; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.v128i8(<128 x i8> %v, i64 0)
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
diff --git a/llvm/test/Analysis/CostModel/RISCV/shuffle-extract_subvector.ll b/llvm/test/Analysis/CostModel/RISCV/shuffle-extract_subvector.ll
index 76cb1955a2b377..793786318a0a16 100644
--- a/llvm/test/Analysis/CostModel/RISCV/shuffle-extract_subvector.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/shuffle-extract_subvector.ll
@@ -9,13 +9,13 @@
define void @test_vXf64(<4 x double> %src256, <8 x double> %src512) {
; CHECK-LABEL: 'test_vXf64'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_01 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_01 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_23 = shufflevector <4 x double> %src256, <4 x double> undef, <2 x i32> <i32 2, i32 3>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_01 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_01 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_23 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_45 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_67 = shufflevector <8 x double> %src512, <8 x double> undef, <2 x i32> <i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_0123 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_0123 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_2345 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_4567 = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of -1 for instruction: %V512_567u = shufflevector <8 x double> %src512, <8 x double> undef, <4 x i32> <i32 5, i32 6, i32 7, i32 poison>
@@ -36,13 +36,13 @@ define void @test_vXf64(<4 x double> %src256, <8 x double> %src512) {
define void @test_vXi64(<4 x i64> %src256, <8 x i64> %src512) {
; CHECK-LABEL: 'test_vXi64'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_01 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_01 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_23 = shufflevector <4 x i64> %src256, <4 x i64> undef, <2 x i32> <i32 2, i32 3>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_01 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_01 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_23 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_45 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_67 = shufflevector <8 x i64> %src512, <8 x i64> undef, <2 x i32> <i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_0123 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_0123 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_2345 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_4567 = shufflevector <8 x i64> %src512, <8 x i64> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
@@ -61,15 +61,15 @@ define void @test_vXi64(<4 x i64> %src256, <8 x i64> %src512) {
define void @test_vXi32(<4 x i32> %src128, <8 x i32> %src256, <16 x i32> %src512) {
; CHECK-LABEL: 'test_vXi32'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_01 = shufflevector <4 x i32> %src128, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V128_01 = shufflevector <4 x i32> %src128, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_23 = shufflevector <4 x i32> %src128, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_01 = shufflevector <8 x i32> %src256, <8 x i32> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_01 = shufflevector <8 x i32> %src256, <8 x i32> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_23 = shufflevector <8 x i32> %src256, <8 x i32> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_45 = shufflevector <8 x i32> %src256, <8 x i32> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_67 = shufflevector <8 x i32> %src256, <8 x i32> undef, <2 x i32> <i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_0123 = shufflevector <8 x i32> %src256, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_0123 = shufflevector <8 x i32> %src256, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_4567 = shufflevector <8 x i32> %src256, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_01 = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_01 = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_23 = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_45 = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_67 = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 6, i32 7>
@@ -77,11 +77,11 @@ define void @test_vXi32(<4 x i32> %src128, <8 x i32> %src256, <16 x i32> %src512
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_AB = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 10, i32 11>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_CD = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 12, i32 13>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_EF = shufflevector <16 x i32> %src512, <16 x i32> undef, <2 x i32> <i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_0123 = shufflevector <16 x i32> %src512, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_0123 = shufflevector <16 x i32> %src512, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_4567 = shufflevector <16 x i32> %src512, <16 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_89AB = shufflevector <16 x i32> %src512, <16 x i32> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_CDEF = shufflevector <16 x i32> %src512, <16 x i32> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_01234567 = shufflevector <16 x i32> %src512, <16 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_01234567 = shufflevector <16 x i32> %src512, <16 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_89ABCDEF = shufflevector <16 x i32> %src512, <16 x i32> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
@@ -112,15 +112,15 @@ define void @test_vXi32(<4 x i32> %src128, <8 x i32> %src256, <16 x i32> %src512
define void @test_vXi16(<4 x i16> %src64, <8 x i16> %src128, <16 x i16> %src256, <32 x i16> %src512) {
; CHECK-LABEL: 'test_vXi16'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_01 = shufflevector <4 x i16> %src64, <4 x i16> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V64_01 = shufflevector <4 x i16> %src64, <4 x i16> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_23 = shufflevector <4 x i16> %src64, <4 x i16> undef, <2 x i32> <i32 2, i32 3>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_01 = shufflevector <8 x i16> %src128, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V128_01 = shufflevector <8 x i16> %src128, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_23 = shufflevector <8 x i16> %src128, <8 x i16> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_45 = shufflevector <8 x i16> %src128, <8 x i16> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_67 = shufflevector <8 x i16> %src128, <8 x i16> undef, <2 x i32> <i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_0123 = shufflevector <8 x i16> %src128, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V128_0123 = shufflevector <8 x i16> %src128, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_4567 = shufflevector <8 x i16> %src128, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_01 = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_01 = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_23 = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_45 = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_67 = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 6, i32 7>
@@ -128,15 +128,15 @@ define void @test_vXi16(<4 x i16> %src64, <8 x i16> %src128, <16 x i16> %src256,
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_AB = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 10, i32 11>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_CD = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 12, i32 13>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_EF = shufflevector <16 x i16> %src256, <16 x i16> undef, <2 x i32> <i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_0123 = shufflevector <16 x i16> %src256, <16 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_0123 = shufflevector <16 x i16> %src256, <16 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_2345 = shufflevector <16 x i16> %src256, <16 x i16> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_4567 = shufflevector <16 x i16> %src256, <16 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_6789 = shufflevector <16 x i16> %src256, <16 x i16> undef, <4 x i32> <i32 6, i32 7, i32 8, i32 9>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_89AB = shufflevector <16 x i16> %src256, <16 x i16> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_CDEF = shufflevector <16 x i16> %src256, <16 x i16> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_01234567 = shufflevector <16 x i16> %src256, <16 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_01234567 = shufflevector <16 x i16> %src256, <16 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_89ABCDEF = shufflevector <16 x i16> %src256, <16 x i16> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01 = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01 = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_02_03 = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_04_05 = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_06_07 = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 6, i32 7>
@@ -152,7 +152,7 @@ define void @test_vXi16(<4 x i16> %src64, <8 x i16> %src128, <16 x i16> %src256,
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_1A_1B = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 26, i32 27>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_1C_1D = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 28, i32 29>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_1E_1F = shufflevector <32 x i16> %src512, <32 x i16> undef, <2 x i32> <i32 30, i32 31>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01_02_03 = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01_02_03 = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_02_03_04_05 = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_04_05_06_07 = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_06_07_08_09 = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 6, i32 7, i32 8, i32 9>
@@ -162,11 +162,11 @@ define void @test_vXi16(<4 x i16> %src64, <8 x i16> %src128, <16 x i16> %src256,
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_14_15_16_17 = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 20, i32 21, i32 22, i32 23>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_18_19_1A_1B = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 24, i32 25, i32 26, i32 27>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_1C_1D_1E_1F = shufflevector <32 x i16> %src512, <32 x i16> undef, <4 x i32> <i32 28, i32 29, i32 30, i32 31>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01_02_03_04_05_06_07 = shufflevector <32 x i16> %src512, <32 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01_02_03_04_05_06_07 = shufflevector <32 x i16> %src512, <32 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_08_09_0A_0B_0C_0D_0E_0F = shufflevector <32 x i16> %src512, <32 x i16> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_10_11_12_13_14_15_16_17 = shufflevector <32 x i16> %src512, <32 x i16> undef, <8 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_18_19_1A_1B_1C_1D_1E_1F = shufflevector <32 x i16> %src512, <32 x i16> undef, <8 x i32> <i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F = shufflevector <32 x i16> %src512, <32 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F = shufflevector <32 x i16> %src512, <32 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_10_11_12_13_14_15_16_17_18_19_1A_1B_1C_1D_1E_1F = shufflevector <32 x i16> %src512, <32 x i16> undef, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
@@ -231,13 +231,13 @@ define void @test_vXi16(<4 x i16> %src64, <8 x i16> %src128, <16 x i16> %src256,
define void @test_vXi8(<8 x i8> %src64, <16 x i8> %src128, <32 x i8> %src256, <64 x i8> %src512) {
; CHECK-LABEL: 'test_vXi8'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_01 = shufflevector <8 x i8> %src64, <8 x i8> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V64_01 = shufflevector <8 x i8> %src64, <8 x i8> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_23 = shufflevector <8 x i8> %src64, <8 x i8> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_45 = shufflevector <8 x i8> %src64, <8 x i8> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_67 = shufflevector <8 x i8> %src64, <8 x i8> undef, <2 x i32> <i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_0123 = shufflevector <8 x i8> %src64, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V64_0123 = shufflevector <8 x i8> %src64, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64_4567 = shufflevector <8 x i8> %src64, <8 x i8> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_01 = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V128_01 = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_23 = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_45 = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_67 = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 6, i32 7>
@@ -245,15 +245,15 @@ define void @test_vXi8(<8 x i8> %src64, <16 x i8> %src128, <32 x i8> %src256, <6
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_AB = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 10, i32 11>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_CD = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 12, i32 13>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_EF = shufflevector <16 x i8> %src128, <16 x i8> undef, <2 x i32> <i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_0123 = shufflevector <16 x i8> %src128, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V128_0123 = shufflevector <16 x i8> %src128, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_2345 = shufflevector <16 x i8> %src128, <16 x i8> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_4567 = shufflevector <16 x i8> %src128, <16 x i8> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_6789 = shufflevector <16 x i8> %src128, <16 x i8> undef, <4 x i32> <i32 6, i32 7, i32 8, i32 9>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_89AB = shufflevector <16 x i8> %src128, <16 x i8> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_CDEF = shufflevector <16 x i8> %src128, <16 x i8> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_01234567 = shufflevector <16 x i8> %src128, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V128_01234567 = shufflevector <16 x i8> %src128, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V128_89ABCDEF = shufflevector <16 x i8> %src128, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_00_01 = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_00_01 = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_02_03 = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_04_05 = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_06_07 = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 6, i32 7>
@@ -269,7 +269,7 @@ define void @test_vXi8(<8 x i8> %src64, <16 x i8> %src128, <32 x i8> %src256, <6
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_1A_1B = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 26, i32 27>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_1C_1D = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 28, i32 29>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_1E_1F = shufflevector <32 x i8> %src256, <32 x i8> undef, <2 x i32> <i32 30, i32 31>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_00_01_02_03 = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_00_01_02_03 = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_02_03_04_05 = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_04_05_06_07 = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_06_07_08_09 = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 6, i32 7, i32 8, i32 9>
@@ -279,13 +279,13 @@ define void @test_vXi8(<8 x i8> %src64, <16 x i8> %src128, <32 x i8> %src256, <6
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_14_15_16_17 = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 20, i32 21, i32 22, i32 23>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_18_19_1A_1B = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 24, i32 25, i32 26, i32 27>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_1C_1D_1E_1F = shufflevector <32 x i8> %src256, <32 x i8> undef, <4 x i32> <i32 28, i32 29, i32 30, i32 31>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_00_01_02_03_04_05_06_07 = shufflevector <32 x i8> %src256, <32 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_00_01_02_03_04_05_06_07 = shufflevector <32 x i8> %src256, <32 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_08_09_0A_0B_0C_0D_0E_0F = shufflevector <32 x i8> %src256, <32 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_10_11_12_13_14_15_16_17 = shufflevector <32 x i8> %src256, <32 x i8> undef, <8 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_18_19_1A_1B_1C_1D_1E_1F = shufflevector <32 x i8> %src256, <32 x i8> undef, <8 x i32> <i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F = shufflevector <32 x i8> %src256, <32 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V256_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F = shufflevector <32 x i8> %src256, <32 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V256_10_11_12_13_14_15_16_17_18_19_1A_1B_1C_1D_1E_1F = shufflevector <32 x i8> %src256, <32 x i8> undef, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01 = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01 = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_02_03 = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_04_05 = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_06_07 = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 6, i32 7>
@@ -317,7 +317,7 @@ define void @test_vXi8(<8 x i8> %src64, <16 x i8> %src128, <32 x i8> %src256, <6
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_3A_3B = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 58, i32 59>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_3C_3D = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 60, i32 61>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_3E_3F = shufflevector <64 x i8> %src512, <64 x i8> undef, <2 x i32> <i32 62, i32 63>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01_02_03 = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01_02_03 = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_04_05_06_07 = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_08_09_0A_0B = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_0C_0D_0E_0F = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
@@ -333,7 +333,7 @@ define void @test_vXi8(<8 x i8> %src64, <16 x i8> %src128, <32 x i8> %src256, <6
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_34_35_36_37 = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 52, i32 53, i32 54, i32 55>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_38_39_3A_3B = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 56, i32 57, i32 58, i32 59>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_3C_3D_3E_3F = shufflevector <64 x i8> %src512, <64 x i8> undef, <4 x i32> <i32 60, i32 61, i32 62, i32 63>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01_02_03_04_05_06_07 = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01_02_03_04_05_06_07 = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_08_09_0A_0B_0C_0D_0E_0F = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_10_11_12_13_14_15_16_17 = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_18_19_1A_1B_1C_1D_1E_1F = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
@@ -341,11 +341,11 @@ define void @test_vXi8(<8 x i8> %src64, <16 x i8> %src128, <32 x i8> %src256, <6
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_28_29_2A_2B_2C_2D_2E_2F = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_30_31_32_33_34_35_36_37 = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_38_39_3A_3B_3C_3D_3E_3F = shufflevector <64 x i8> %src512, <64 x i8> undef, <8 x i32> <i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F = shufflevector <64 x i8> %src512, <64 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F = shufflevector <64 x i8> %src512, <64 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_10_11_12_13_14_15_16_17_18_19_1A_1B_1C_1D_1E_1F = shufflevector <64 x i8> %src512, <64 x i8> undef, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_20_21_22_23_24_25_26_27_28_29_2A_2B_2C_2D_2E_2F = shufflevector <64 x i8> %src512, <64 x i8> undef, <16 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_30_31_32_33_34_35_36_37_38_39_3A_3B_3C_3D_3E_3F = shufflevector <64 x i8> %src512, <64 x i8> undef, <16 x i32> <i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F_10_11_12_13_14_15_16_17_18_19_1A_1B_1C_1D_1E_1F = shufflevector <64 x i8> %src512, <64 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V512_00_01_02_03_04_05_06_07_08_09_0A_0B_0C_0D_0E_0F_10_11_12_13_14_15_16_17_18_19_1A_1B_1C_1D_1E_1F = shufflevector <64 x i8> %src512, <64 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V512_20_21_22_23_24_25_26_27_28_29_2A_2B_2C_2D_2E_2F_30_31_32_33_34_35_36_37_38_39_3A_3B_3C_3D_3E_3F = shufflevector <64 x i8> %src512, <64 x i8> undef, <32 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
diff --git a/llvm/test/CodeGen/AArch64/arm64-stur.ll b/llvm/test/CodeGen/AArch64/arm64-stur.ll
index 2a74abb10226da..7d9de9e28ff5c0 100644
--- a/llvm/test/CodeGen/AArch64/arm64-stur.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-stur.ll
@@ -65,9 +65,8 @@ declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind
; CHECK-LABEL: unaligned:
; CHECK-NOT: str q0
-; CHECK: str d[[REG:[0-9]+]], [x0]
-; CHECK: ext.16b v[[REG2:[0-9]+]], v[[REG]], v[[REG]], #8
-; CHECK: str d[[REG2]], [x0, #8]
+; CHECK: ext.16b v[[REG2:[0-9]+]], v[[REG:[0-9]+]], v[[REG]], #8
+; CHECK: stp d[[REG]], d[[REG2]], [x0]
define void @unaligned(ptr %p, <4 x i32> %v) nounwind {
store <4 x i32> %v, ptr %p, align 4
ret void
diff --git a/llvm/test/CodeGen/AArch64/merge-store.ll b/llvm/test/CodeGen/AArch64/merge-store.ll
index b93d0c3bc96086..6653984562ae6d 100644
--- a/llvm/test/CodeGen/AArch64/merge-store.ll
+++ b/llvm/test/CodeGen/AArch64/merge-store.ll
@@ -45,8 +45,7 @@ define void @merge_vec_extract_stores(<4 x float> %v1, ptr %ptr) {
; SPLITTING-LABEL: merge_vec_extract_stores:
; SPLITTING: // %bb.0:
; SPLITTING-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; SPLITTING-NEXT: str d0, [x0, #24]
-; SPLITTING-NEXT: str d1, [x0, #32]
+; SPLITTING-NEXT: stp d0, d1, [x0, #24]
; SPLITTING-NEXT: ret
;
; MISALIGNED-LABEL: merge_vec_extract_stores:
diff --git a/llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll b/llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll
index 6d1986ebb8182b..93fb9c1bc4b9d0 100644
--- a/llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll
+++ b/llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll
@@ -1,72 +1,56 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64 -mcpu=cortex-a55 -mattr=+store-pair-suppress -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -mcpu=apple-m1 -mattr=+store-pair-suppress -o - %s | FileCheck %s
; Check that stp are not suppressed at minsize.
-%T_IN_BLOCK = type [ 2 x { double, { double, double } } ]
-declare %T_IN_BLOCK @return_in_block()
- at in_block_store = dso_local global %T_IN_BLOCK zeroinitializer, align 8
-
-define void @test_default() uwtable {
+define void @test_default(ptr %dst, <8 x i32> %v0) {
; CHECK-LABEL: test_default:
-; CHECK: // %bb.0:
-; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: .cfi_offset w30, -16
-; CHECK-NEXT: bl return_in_block
-; CHECK-NEXT: adrp x8, in_block_store
-; CHECK-NEXT: add x8, x8, :lo12:in_block_store
-; CHECK-NEXT: str d0, [x8]
-; CHECK-NEXT: str d1, [x8, #8]
-; CHECK-NEXT: str d2, [x8, #16]
-; CHECK-NEXT: str d3, [x8, #24]
-; CHECK-NEXT: str d4, [x8, #32]
-; CHECK-NEXT: str d5, [x8, #40]
-; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-NEXT: .cfi_def_cfa_offset 0
-; CHECK-NEXT: .cfi_restore w30
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: mul v1.8b, v0.8b, v0.8b
+; CHECK-NEXT: str d1, [x0, #8]
+; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
- %1 = call %T_IN_BLOCK @return_in_block()
- store %T_IN_BLOCK %1, ptr @in_block_store
+entry:
+ %add.ptr.1 = getelementptr i8, ptr %dst, i64 8
+ %t = trunc <8 x i32> %v0 to <8 x i8>
+ %mul = mul <8 x i8> %t, %t
+ store <8 x i8> %mul, ptr %add.ptr.1, align 1
+ store <8 x i8> %t, ptr %dst, align 1
ret void
}
-define void @test_minsize() minsize uwtable {
+define void @test_minsize(ptr %dst, <8 x i32> %v0) minsize {
; CHECK-LABEL: test_minsize:
-; CHECK: // %bb.0:
-; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: .cfi_offset w30, -16
-; CHECK-NEXT: bl return_in_block
-; CHECK-NEXT: adrp x8, in_block_store
-; CHECK-NEXT: add x8, x8, :lo12:in_block_store
-; CHECK-NEXT: stp d0, d1, [x8]
-; CHECK-NEXT: stp d2, d3, [x8, #16]
-; CHECK-NEXT: stp d4, d5, [x8, #32]
-; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: mul v1.8b, v0.8b, v0.8b
+; CHECK-NEXT: stp d0, d1, [x0]
; CHECK-NEXT: ret
- %1 = call %T_IN_BLOCK @return_in_block()
- store %T_IN_BLOCK %1, ptr @in_block_store
+entry:
+ %add.ptr.1 = getelementptr i8, ptr %dst, i64 8
+ %t = trunc <8 x i32> %v0 to <8 x i8>
+ %mul = mul <8 x i8> %t, %t
+ store <8 x i8> %mul, ptr %add.ptr.1, align 1
+ store <8 x i8> %t, ptr %dst, align 1
ret void
}
-define void @test_optsize() optsize uwtable {
+define void @test_optsize(ptr %dst, <8 x i32> %v0) optsize {
; CHECK-LABEL: test_optsize:
-; CHECK: // %bb.0:
-; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: .cfi_offset w30, -16
-; CHECK-NEXT: bl return_in_block
-; CHECK-NEXT: adrp x8, in_block_store
-; CHECK-NEXT: add x8, x8, :lo12:in_block_store
-; CHECK-NEXT: stp d0, d1, [x8]
-; CHECK-NEXT: stp d2, d3, [x8, #16]
-; CHECK-NEXT: stp d4, d5, [x8, #32]
-; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-NEXT: .cfi_def_cfa_offset 0
-; CHECK-NEXT: .cfi_restore w30
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: mul v1.8b, v0.8b, v0.8b
+; CHECK-NEXT: stp d0, d1, [x0]
; CHECK-NEXT: ret
- %1 = call %T_IN_BLOCK @return_in_block()
- store %T_IN_BLOCK %1, ptr @in_block_store
+entry:
+ %add.ptr.1 = getelementptr i8, ptr %dst, i64 8
+ %t = trunc <8 x i32> %v0 to <8 x i8>
+ %mul = mul <8 x i8> %t, %t
+ store <8 x i8> %mul, ptr %add.ptr.1, align 1
+ store <8 x i8> %t, ptr %dst, align 1
ret void
}
diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
index a8477cc550fe6a..90d78779b764d2 100644
--- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
@@ -7,6 +7,8 @@
; RUN: | FileCheck -check-prefixes=NOZACAS,RV64IA %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=ZACAS,RV64IA-ZACAS %s
+; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas,+experimental-zabha -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=ZACAS,RV64IA-ZABHA %s
; Test cmpxchg followed by a branch on the cmpxchg success value to see if the
; branch is folded into the cmpxchg expansion.
@@ -209,6 +211,16 @@ define void @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %v
; RV64IA-ZACAS-NEXT: # %bb.5: # %do_cmpxchg
; RV64IA-ZACAS-NEXT: # %bb.2: # %exit
; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-ZABHA-LABEL: cmpxchg_masked_and_branch1:
+; RV64IA-ZABHA: # %bb.0: # %entry
+; RV64IA-ZABHA-NEXT: .LBB2_1: # %do_cmpxchg
+; RV64IA-ZABHA-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZABHA-NEXT: mv a3, a1
+; RV64IA-ZABHA-NEXT: amocas.b.aqrl a3, a2, (a0)
+; RV64IA-ZABHA-NEXT: bne a3, a1, .LBB2_1
+; RV64IA-ZABHA-NEXT: # %bb.2: # %exit
+; RV64IA-ZABHA-NEXT: ret
entry:
br label %do_cmpxchg
do_cmpxchg:
@@ -351,6 +363,16 @@ define void @cmpxchg_masked_and_branch2(ptr %ptr, i8 signext %cmp, i8 signext %v
; RV64IA-ZACAS-NEXT: beq a1, a4, .LBB3_1
; RV64IA-ZACAS-NEXT: # %bb.2: # %exit
; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-ZABHA-LABEL: cmpxchg_masked_and_branch2:
+; RV64IA-ZABHA: # %bb.0: # %entry
+; RV64IA-ZABHA-NEXT: .LBB3_1: # %do_cmpxchg
+; RV64IA-ZABHA-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZABHA-NEXT: mv a3, a1
+; RV64IA-ZABHA-NEXT: amocas.b.aqrl a3, a2, (a0)
+; RV64IA-ZABHA-NEXT: beq a3, a1, .LBB3_1
+; RV64IA-ZABHA-NEXT: # %bb.2: # %exit
+; RV64IA-ZABHA-NEXT: ret
entry:
br label %do_cmpxchg
do_cmpxchg:
diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
index 5b3e5789e8d910..8df37bf40975c1 100644
--- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
@@ -15,10 +15,14 @@
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-WMO-ZACAS %s
+; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zacas,+experimental-zabha -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZABHA,RV64IA-WMO-ZABHA %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+experimental-zacas -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-TSO-ZACAS %s
+; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+experimental-zacas,+experimental-zabha -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZABHA,RV64IA-TSO-ZABHA %s
define void @cmpxchg_i8_monotonic_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV32I-LABEL: cmpxchg_i8_monotonic_monotonic:
@@ -70,28 +74,79 @@ define void @cmpxchg_i8_monotonic_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i8_monotonic_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a4, 255
-; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
-; RV64IA-NEXT: sllw a0, a2, a0
-; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a2, (a3)
-; RV64IA-NEXT: and a5, a2, a4
-; RV64IA-NEXT: bne a5, a1, .LBB0_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
-; RV64IA-NEXT: xor a5, a2, a0
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a2, a5
-; RV64IA-NEXT: sc.w a5, a5, (a3)
-; RV64IA-NEXT: bnez a5, .LBB0_1
-; RV64IA-NEXT: .LBB0_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i8_monotonic_monotonic:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a3, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a4, 255
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: andi a2, a2, 255
+; RV64IA-WMO-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a2, (a3)
+; RV64IA-WMO-NEXT: and a5, a2, a4
+; RV64IA-WMO-NEXT: bne a5, a1, .LBB0_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a2, a0
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a2, a5
+; RV64IA-WMO-NEXT: sc.w a5, a5, (a3)
+; RV64IA-WMO-NEXT: bnez a5, .LBB0_1
+; RV64IA-WMO-NEXT: .LBB0_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: cmpxchg_i8_monotonic_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a4, 255
+; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-ZACAS-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB0_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a3)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB0_1
+; RV64IA-ZACAS-NEXT: .LBB0_3:
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-ZABHA-LABEL: cmpxchg_i8_monotonic_monotonic:
+; RV64IA-ZABHA: # %bb.0:
+; RV64IA-ZABHA-NEXT: amocas.b a1, a2, (a0)
+; RV64IA-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i8_monotonic_monotonic:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a3, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a4, 255
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: andi a2, a2, 255
+; RV64IA-TSO-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a2, (a3)
+; RV64IA-TSO-NEXT: and a5, a2, a4
+; RV64IA-TSO-NEXT: bne a5, a1, .LBB0_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a2, a0
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a2, a5
+; RV64IA-TSO-NEXT: sc.w a5, a5, (a3)
+; RV64IA-TSO-NEXT: bnez a5, .LBB0_1
+; RV64IA-TSO-NEXT: .LBB0_3:
+; RV64IA-TSO-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val monotonic monotonic
ret void
}
@@ -261,6 +316,11 @@ define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-ZACAS-NEXT: .LBB1_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_acquire_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.b.aq a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i8_acquire_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -306,6 +366,11 @@ define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB1_1
; RV64IA-TSO-ZACAS-NEXT: .LBB1_3:
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_acquire_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire monotonic
ret void
}
@@ -475,6 +540,11 @@ define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-ZACAS-NEXT: .LBB2_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_acquire_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.b.aq a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i8_acquire_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -520,6 +590,11 @@ define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB2_1
; RV64IA-TSO-ZACAS-NEXT: .LBB2_3:
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_acquire_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire acquire
ret void
}
@@ -689,6 +764,11 @@ define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-ZACAS-NEXT: .LBB3_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_release_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.b.rl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i8_release_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -734,6 +814,11 @@ define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB3_1
; RV64IA-TSO-ZACAS-NEXT: .LBB3_3:
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_release_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release monotonic
ret void
}
@@ -903,6 +988,11 @@ define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-ZACAS-NEXT: .LBB4_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_release_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.b.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i8_release_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -948,6 +1038,11 @@ define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB4_1
; RV64IA-TSO-ZACAS-NEXT: .LBB4_3:
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_release_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release acquire
ret void
}
@@ -1117,6 +1212,11 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-ZACAS-NEXT: .LBB5_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_acq_rel_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.b.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i8_acq_rel_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -1162,6 +1262,11 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB5_1
; RV64IA-TSO-ZACAS-NEXT: .LBB5_3:
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_acq_rel_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel monotonic
ret void
}
@@ -1331,6 +1436,11 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-WMO-ZACAS-NEXT: .LBB6_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_acq_rel_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.b.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i8_acq_rel_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -1376,6 +1486,11 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB6_1
; RV64IA-TSO-ZACAS-NEXT: .LBB6_3:
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_acq_rel_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel acquire
ret void
}
@@ -1430,28 +1545,84 @@ define void @cmpxchg_i8_seq_cst_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i8_seq_cst_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a4, 255
-; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
-; RV64IA-NEXT: sllw a0, a2, a0
-; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-NEXT: and a5, a2, a4
-; RV64IA-NEXT: bne a5, a1, .LBB7_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
-; RV64IA-NEXT: xor a5, a2, a0
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a2, a5
-; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
-; RV64IA-NEXT: bnez a5, .LBB7_1
-; RV64IA-NEXT: .LBB7_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i8_seq_cst_monotonic:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a3, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a4, 255
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: andi a2, a2, 255
+; RV64IA-WMO-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-WMO-NEXT: and a5, a2, a4
+; RV64IA-WMO-NEXT: bne a5, a1, .LBB7_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a2, a0
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a2, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-WMO-NEXT: bnez a5, .LBB7_1
+; RV64IA-WMO-NEXT: .LBB7_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: cmpxchg_i8_seq_cst_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a4, 255
+; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-ZACAS-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB7_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB7_1
+; RV64IA-ZACAS-NEXT: .LBB7_3:
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_seq_cst_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.b.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i8_seq_cst_monotonic:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a3, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a4, 255
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: andi a2, a2, 255
+; RV64IA-TSO-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-TSO-NEXT: and a5, a2, a4
+; RV64IA-TSO-NEXT: bne a5, a1, .LBB7_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a2, a0
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a2, a5
+; RV64IA-TSO-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-TSO-NEXT: bnez a5, .LBB7_1
+; RV64IA-TSO-NEXT: .LBB7_3:
+; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_seq_cst_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst monotonic
ret void
}
@@ -1506,28 +1677,84 @@ define void @cmpxchg_i8_seq_cst_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i8_seq_cst_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a4, 255
-; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
-; RV64IA-NEXT: sllw a0, a2, a0
-; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-NEXT: and a5, a2, a4
-; RV64IA-NEXT: bne a5, a1, .LBB8_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
-; RV64IA-NEXT: xor a5, a2, a0
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a2, a5
-; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
-; RV64IA-NEXT: bnez a5, .LBB8_1
-; RV64IA-NEXT: .LBB8_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i8_seq_cst_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a3, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a4, 255
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: andi a2, a2, 255
+; RV64IA-WMO-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-WMO-NEXT: and a5, a2, a4
+; RV64IA-WMO-NEXT: bne a5, a1, .LBB8_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a2, a0
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a2, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-WMO-NEXT: bnez a5, .LBB8_1
+; RV64IA-WMO-NEXT: .LBB8_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: cmpxchg_i8_seq_cst_acquire:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a4, 255
+; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-ZACAS-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB8_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB8_1
+; RV64IA-ZACAS-NEXT: .LBB8_3:
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_seq_cst_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.b.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i8_seq_cst_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a3, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a4, 255
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: andi a2, a2, 255
+; RV64IA-TSO-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-TSO-NEXT: and a5, a2, a4
+; RV64IA-TSO-NEXT: bne a5, a1, .LBB8_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a2, a0
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a2, a5
+; RV64IA-TSO-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-TSO-NEXT: bnez a5, .LBB8_1
+; RV64IA-TSO-NEXT: .LBB8_3:
+; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_seq_cst_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst acquire
ret void
}
@@ -1582,28 +1809,84 @@ define void @cmpxchg_i8_seq_cst_seq_cst(ptr %ptr, i8 %cmp, i8 %val) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a4, 255
-; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: andi a2, a2, 255
-; RV64IA-NEXT: sllw a0, a2, a0
-; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-NEXT: and a5, a2, a4
-; RV64IA-NEXT: bne a5, a1, .LBB9_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
-; RV64IA-NEXT: xor a5, a2, a0
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a2, a5
-; RV64IA-NEXT: sc.w.rl a5, a5, (a3)
-; RV64IA-NEXT: bnez a5, .LBB9_1
-; RV64IA-NEXT: .LBB9_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i8_seq_cst_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a3, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a4, 255
+; RV64IA-WMO-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: andi a2, a2, 255
+; RV64IA-WMO-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-WMO-NEXT: and a5, a2, a4
+; RV64IA-WMO-NEXT: bne a5, a1, .LBB9_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
+; RV64IA-WMO-NEXT: xor a5, a2, a0
+; RV64IA-WMO-NEXT: and a5, a5, a4
+; RV64IA-WMO-NEXT: xor a5, a2, a5
+; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-WMO-NEXT: bnez a5, .LBB9_1
+; RV64IA-WMO-NEXT: .LBB9_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: cmpxchg_i8_seq_cst_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a4, 255
+; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: andi a2, a2, 255
+; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-ZACAS-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-ZACAS-NEXT: and a5, a2, a4
+; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB9_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a5, a2, a0
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a2, a5
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB9_1
+; RV64IA-ZACAS-NEXT: .LBB9_3:
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.b.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i8_seq_cst_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a3, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a4, 255
+; RV64IA-TSO-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: andi a2, a2, 255
+; RV64IA-TSO-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-TSO-NEXT: and a5, a2, a4
+; RV64IA-TSO-NEXT: bne a5, a1, .LBB9_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
+; RV64IA-TSO-NEXT: xor a5, a2, a0
+; RV64IA-TSO-NEXT: and a5, a5, a4
+; RV64IA-TSO-NEXT: xor a5, a2, a5
+; RV64IA-TSO-NEXT: sc.w.rl a5, a5, (a3)
+; RV64IA-TSO-NEXT: bnez a5, .LBB9_1
+; RV64IA-TSO-NEXT: .LBB9_3:
+; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.b a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst seq_cst
ret void
}
@@ -1659,29 +1942,82 @@ define void @cmpxchg_i16_monotonic_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounw
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i16_monotonic_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a4, 16
-; RV64IA-NEXT: addi a4, a4, -1
-; RV64IA-NEXT: sllw a5, a4, a0
-; RV64IA-NEXT: and a1, a1, a4
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: and a2, a2, a4
-; RV64IA-NEXT: sllw a0, a2, a0
-; RV64IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a2, (a3)
-; RV64IA-NEXT: and a4, a2, a5
-; RV64IA-NEXT: bne a4, a1, .LBB10_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
-; RV64IA-NEXT: xor a4, a2, a0
-; RV64IA-NEXT: and a4, a4, a5
-; RV64IA-NEXT: xor a4, a2, a4
-; RV64IA-NEXT: sc.w a4, a4, (a3)
-; RV64IA-NEXT: bnez a4, .LBB10_1
-; RV64IA-NEXT: .LBB10_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i16_monotonic_monotonic:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a3, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a4, 16
+; RV64IA-WMO-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NEXT: sllw a5, a4, a0
+; RV64IA-WMO-NEXT: and a1, a1, a4
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: and a2, a2, a4
+; RV64IA-WMO-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w a2, (a3)
+; RV64IA-WMO-NEXT: and a4, a2, a5
+; RV64IA-WMO-NEXT: bne a4, a1, .LBB10_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
+; RV64IA-WMO-NEXT: xor a4, a2, a0
+; RV64IA-WMO-NEXT: and a4, a4, a5
+; RV64IA-WMO-NEXT: xor a4, a2, a4
+; RV64IA-WMO-NEXT: sc.w a4, a4, (a3)
+; RV64IA-WMO-NEXT: bnez a4, .LBB10_1
+; RV64IA-WMO-NEXT: .LBB10_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: cmpxchg_i16_monotonic_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a4, 16
+; RV64IA-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-ZACAS-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a2, (a3)
+; RV64IA-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-ZACAS-NEXT: bne a4, a1, .LBB10_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-ZACAS-NEXT: sc.w a4, a4, (a3)
+; RV64IA-ZACAS-NEXT: bnez a4, .LBB10_1
+; RV64IA-ZACAS-NEXT: .LBB10_3:
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-ZABHA-LABEL: cmpxchg_i16_monotonic_monotonic:
+; RV64IA-ZABHA: # %bb.0:
+; RV64IA-ZABHA-NEXT: amocas.h a1, a2, (a0)
+; RV64IA-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i16_monotonic_monotonic:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a3, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a4, 16
+; RV64IA-TSO-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NEXT: sllw a5, a4, a0
+; RV64IA-TSO-NEXT: and a1, a1, a4
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: and a2, a2, a4
+; RV64IA-TSO-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w a2, (a3)
+; RV64IA-TSO-NEXT: and a4, a2, a5
+; RV64IA-TSO-NEXT: bne a4, a1, .LBB10_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
+; RV64IA-TSO-NEXT: xor a4, a2, a0
+; RV64IA-TSO-NEXT: and a4, a4, a5
+; RV64IA-TSO-NEXT: xor a4, a2, a4
+; RV64IA-TSO-NEXT: sc.w a4, a4, (a3)
+; RV64IA-TSO-NEXT: bnez a4, .LBB10_1
+; RV64IA-TSO-NEXT: .LBB10_3:
+; RV64IA-TSO-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val monotonic monotonic
ret void
}
@@ -1857,6 +2193,11 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: .LBB11_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_acquire_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.h.aq a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i16_acquire_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -1904,6 +2245,11 @@ define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB11_1
; RV64IA-TSO-ZACAS-NEXT: .LBB11_3:
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_acquire_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire monotonic
ret void
}
@@ -2079,6 +2425,11 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: .LBB12_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_acquire_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.h.aq a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i16_acquire_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -2126,6 +2477,11 @@ define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB12_1
; RV64IA-TSO-ZACAS-NEXT: .LBB12_3:
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_acquire_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire acquire
ret void
}
@@ -2301,6 +2657,11 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: .LBB13_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_release_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.h.rl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i16_release_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -2348,6 +2709,11 @@ define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB13_1
; RV64IA-TSO-ZACAS-NEXT: .LBB13_3:
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_release_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release monotonic
ret void
}
@@ -2523,6 +2889,11 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: .LBB14_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_release_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.h.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i16_release_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -2570,6 +2941,11 @@ define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB14_1
; RV64IA-TSO-ZACAS-NEXT: .LBB14_3:
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_release_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release acquire
ret void
}
@@ -2745,6 +3121,11 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: .LBB15_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_acq_rel_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.h.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i16_acq_rel_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -2792,6 +3173,11 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB15_1
; RV64IA-TSO-ZACAS-NEXT: .LBB15_3:
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_acq_rel_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel monotonic
ret void
}
@@ -2967,6 +3353,11 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: .LBB16_3:
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_acq_rel_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.h.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i16_acq_rel_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: andi a3, a0, -4
@@ -3014,6 +3405,11 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64IA-TSO-ZACAS-NEXT: bnez a4, .LBB16_1
; RV64IA-TSO-ZACAS-NEXT: .LBB16_3:
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_acq_rel_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel acquire
ret void
}
@@ -3069,29 +3465,87 @@ define void @cmpxchg_i16_seq_cst_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwin
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i16_seq_cst_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a4, 16
-; RV64IA-NEXT: addi a4, a4, -1
-; RV64IA-NEXT: sllw a5, a4, a0
-; RV64IA-NEXT: and a1, a1, a4
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: and a2, a2, a4
-; RV64IA-NEXT: sllw a0, a2, a0
-; RV64IA-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-NEXT: and a4, a2, a5
-; RV64IA-NEXT: bne a4, a1, .LBB17_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
-; RV64IA-NEXT: xor a4, a2, a0
-; RV64IA-NEXT: and a4, a4, a5
-; RV64IA-NEXT: xor a4, a2, a4
-; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
-; RV64IA-NEXT: bnez a4, .LBB17_1
-; RV64IA-NEXT: .LBB17_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i16_seq_cst_monotonic:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a3, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a4, 16
+; RV64IA-WMO-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NEXT: sllw a5, a4, a0
+; RV64IA-WMO-NEXT: and a1, a1, a4
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: and a2, a2, a4
+; RV64IA-WMO-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-WMO-NEXT: and a4, a2, a5
+; RV64IA-WMO-NEXT: bne a4, a1, .LBB17_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
+; RV64IA-WMO-NEXT: xor a4, a2, a0
+; RV64IA-WMO-NEXT: and a4, a4, a5
+; RV64IA-WMO-NEXT: xor a4, a2, a4
+; RV64IA-WMO-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-WMO-NEXT: bnez a4, .LBB17_1
+; RV64IA-WMO-NEXT: .LBB17_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: cmpxchg_i16_seq_cst_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a4, 16
+; RV64IA-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-ZACAS-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-ZACAS-NEXT: bne a4, a1, .LBB17_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-ZACAS-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-ZACAS-NEXT: bnez a4, .LBB17_1
+; RV64IA-ZACAS-NEXT: .LBB17_3:
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_seq_cst_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.h.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i16_seq_cst_monotonic:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a3, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a4, 16
+; RV64IA-TSO-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NEXT: sllw a5, a4, a0
+; RV64IA-TSO-NEXT: and a1, a1, a4
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: and a2, a2, a4
+; RV64IA-TSO-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-TSO-NEXT: and a4, a2, a5
+; RV64IA-TSO-NEXT: bne a4, a1, .LBB17_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
+; RV64IA-TSO-NEXT: xor a4, a2, a0
+; RV64IA-TSO-NEXT: and a4, a4, a5
+; RV64IA-TSO-NEXT: xor a4, a2, a4
+; RV64IA-TSO-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-TSO-NEXT: bnez a4, .LBB17_1
+; RV64IA-TSO-NEXT: .LBB17_3:
+; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_seq_cst_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst monotonic
ret void
}
@@ -3147,29 +3601,87 @@ define void @cmpxchg_i16_seq_cst_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i16_seq_cst_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a4, 16
-; RV64IA-NEXT: addi a4, a4, -1
-; RV64IA-NEXT: sllw a5, a4, a0
-; RV64IA-NEXT: and a1, a1, a4
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: and a2, a2, a4
-; RV64IA-NEXT: sllw a0, a2, a0
-; RV64IA-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-NEXT: and a4, a2, a5
-; RV64IA-NEXT: bne a4, a1, .LBB18_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
-; RV64IA-NEXT: xor a4, a2, a0
-; RV64IA-NEXT: and a4, a4, a5
-; RV64IA-NEXT: xor a4, a2, a4
-; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
-; RV64IA-NEXT: bnez a4, .LBB18_1
-; RV64IA-NEXT: .LBB18_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i16_seq_cst_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a3, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a4, 16
+; RV64IA-WMO-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NEXT: sllw a5, a4, a0
+; RV64IA-WMO-NEXT: and a1, a1, a4
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: and a2, a2, a4
+; RV64IA-WMO-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-WMO-NEXT: and a4, a2, a5
+; RV64IA-WMO-NEXT: bne a4, a1, .LBB18_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
+; RV64IA-WMO-NEXT: xor a4, a2, a0
+; RV64IA-WMO-NEXT: and a4, a4, a5
+; RV64IA-WMO-NEXT: xor a4, a2, a4
+; RV64IA-WMO-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-WMO-NEXT: bnez a4, .LBB18_1
+; RV64IA-WMO-NEXT: .LBB18_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: cmpxchg_i16_seq_cst_acquire:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a4, 16
+; RV64IA-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-ZACAS-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-ZACAS-NEXT: bne a4, a1, .LBB18_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-ZACAS-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-ZACAS-NEXT: bnez a4, .LBB18_1
+; RV64IA-ZACAS-NEXT: .LBB18_3:
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_seq_cst_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.h.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i16_seq_cst_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a3, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a4, 16
+; RV64IA-TSO-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NEXT: sllw a5, a4, a0
+; RV64IA-TSO-NEXT: and a1, a1, a4
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: and a2, a2, a4
+; RV64IA-TSO-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-TSO-NEXT: and a4, a2, a5
+; RV64IA-TSO-NEXT: bne a4, a1, .LBB18_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
+; RV64IA-TSO-NEXT: xor a4, a2, a0
+; RV64IA-TSO-NEXT: and a4, a4, a5
+; RV64IA-TSO-NEXT: xor a4, a2, a4
+; RV64IA-TSO-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-TSO-NEXT: bnez a4, .LBB18_1
+; RV64IA-TSO-NEXT: .LBB18_3:
+; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_seq_cst_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst acquire
ret void
}
@@ -3225,29 +3737,87 @@ define void @cmpxchg_i16_seq_cst_seq_cst(ptr %ptr, i16 %cmp, i16 %val) nounwind
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a3, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a4, 16
-; RV64IA-NEXT: addi a4, a4, -1
-; RV64IA-NEXT: sllw a5, a4, a0
-; RV64IA-NEXT: and a1, a1, a4
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: and a2, a2, a4
-; RV64IA-NEXT: sllw a0, a2, a0
-; RV64IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a2, (a3)
-; RV64IA-NEXT: and a4, a2, a5
-; RV64IA-NEXT: bne a4, a1, .LBB19_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
-; RV64IA-NEXT: xor a4, a2, a0
-; RV64IA-NEXT: and a4, a4, a5
-; RV64IA-NEXT: xor a4, a2, a4
-; RV64IA-NEXT: sc.w.rl a4, a4, (a3)
-; RV64IA-NEXT: bnez a4, .LBB19_1
-; RV64IA-NEXT: .LBB19_3:
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: cmpxchg_i16_seq_cst_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a3, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: lui a4, 16
+; RV64IA-WMO-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NEXT: sllw a5, a4, a0
+; RV64IA-WMO-NEXT: and a1, a1, a4
+; RV64IA-WMO-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NEXT: and a2, a2, a4
+; RV64IA-WMO-NEXT: sllw a0, a2, a0
+; RV64IA-WMO-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-WMO-NEXT: and a4, a2, a5
+; RV64IA-WMO-NEXT: bne a4, a1, .LBB19_3
+; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
+; RV64IA-WMO-NEXT: xor a4, a2, a0
+; RV64IA-WMO-NEXT: and a4, a4, a5
+; RV64IA-WMO-NEXT: xor a4, a2, a4
+; RV64IA-WMO-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-WMO-NEXT: bnez a4, .LBB19_1
+; RV64IA-WMO-NEXT: .LBB19_3:
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: cmpxchg_i16_seq_cst_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a3, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a4, 16
+; RV64IA-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-ZACAS-NEXT: sllw a5, a4, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a4
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: and a2, a2, a4
+; RV64IA-ZACAS-NEXT: sllw a0, a2, a0
+; RV64IA-ZACAS-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-ZACAS-NEXT: and a4, a2, a5
+; RV64IA-ZACAS-NEXT: bne a4, a1, .LBB19_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a4, a2, a0
+; RV64IA-ZACAS-NEXT: and a4, a4, a5
+; RV64IA-ZACAS-NEXT: xor a4, a2, a4
+; RV64IA-ZACAS-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-ZACAS-NEXT: bnez a4, .LBB19_1
+; RV64IA-ZACAS-NEXT: .LBB19_3:
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.h.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-LABEL: cmpxchg_i16_seq_cst_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a3, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: lui a4, 16
+; RV64IA-TSO-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NEXT: sllw a5, a4, a0
+; RV64IA-TSO-NEXT: and a1, a1, a4
+; RV64IA-TSO-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NEXT: and a2, a2, a4
+; RV64IA-TSO-NEXT: sllw a0, a2, a0
+; RV64IA-TSO-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NEXT: lr.w.aqrl a2, (a3)
+; RV64IA-TSO-NEXT: and a4, a2, a5
+; RV64IA-TSO-NEXT: bne a4, a1, .LBB19_3
+; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
+; RV64IA-TSO-NEXT: xor a4, a2, a0
+; RV64IA-TSO-NEXT: and a4, a4, a5
+; RV64IA-TSO-NEXT: xor a4, a2, a4
+; RV64IA-TSO-NEXT: sc.w.rl a4, a4, (a3)
+; RV64IA-TSO-NEXT: bnez a4, .LBB19_1
+; RV64IA-TSO-NEXT: .LBB19_3:
+; RV64IA-TSO-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.h a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst seq_cst
ret void
}
@@ -3323,6 +3893,11 @@ define void @cmpxchg_i32_monotonic_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounw
; RV64IA-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-ZACAS-NEXT: ret
;
+; RV64IA-ZABHA-LABEL: cmpxchg_i32_monotonic_monotonic:
+; RV64IA-ZABHA: # %bb.0:
+; RV64IA-ZABHA-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_monotonic_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -3414,6 +3989,11 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aq a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_acquire_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.w.aq a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_acquire_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -3430,6 +4010,11 @@ define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_acquire_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acquire monotonic
ret void
}
@@ -3510,6 +4095,11 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aq a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_acquire_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.w.aq a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_acquire_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -3526,6 +4116,11 @@ define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_acquire_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acquire acquire
ret void
}
@@ -3606,6 +4201,11 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.w.rl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_release_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.w.rl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_release_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -3622,6 +4222,11 @@ define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_release_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release monotonic
ret void
}
@@ -3702,6 +4307,11 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_release_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_release_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -3718,6 +4328,11 @@ define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_release_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release acquire
ret void
}
@@ -3798,6 +4413,11 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_acq_rel_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_acq_rel_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -3814,6 +4434,11 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_acq_rel_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel monotonic
ret void
}
@@ -3894,6 +4519,11 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_acq_rel_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_acq_rel_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -3910,6 +4540,11 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_acq_rel_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel acquire
ret void
}
@@ -3990,6 +4625,11 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_seq_cst_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_seq_cst_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -4006,6 +4646,11 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_seq_cst_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst monotonic
ret void
}
@@ -4086,6 +4731,11 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_seq_cst_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_seq_cst_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -4102,6 +4752,11 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_seq_cst_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst acquire
ret void
}
@@ -4182,6 +4837,11 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.w.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.w.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: sext.w a1, a1
@@ -4198,6 +4858,11 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.w a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.w a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst
ret void
}
@@ -4264,6 +4929,11 @@ define void @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounw
; RV64IA-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-ZACAS-NEXT: ret
;
+; RV64IA-ZABHA-LABEL: cmpxchg_i64_monotonic_monotonic:
+; RV64IA-ZABHA: # %bb.0:
+; RV64IA-ZABHA-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_monotonic_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
@@ -4342,6 +5012,11 @@ define void @cmpxchg_i64_acquire_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aq a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_acquire_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.d.aq a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_acquire_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
@@ -4357,6 +5032,11 @@ define void @cmpxchg_i64_acquire_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_acquire_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acquire monotonic
ret void
}
@@ -4425,6 +5105,11 @@ define void @cmpxchg_i64_acquire_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aq a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_acquire_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.d.aq a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_acquire_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
@@ -4440,6 +5125,11 @@ define void @cmpxchg_i64_acquire_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_acquire_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acquire acquire
ret void
}
@@ -4508,6 +5198,11 @@ define void @cmpxchg_i64_release_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.d.rl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_release_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.d.rl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_release_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
@@ -4523,6 +5218,11 @@ define void @cmpxchg_i64_release_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_release_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val release monotonic
ret void
}
@@ -4591,6 +5291,11 @@ define void @cmpxchg_i64_release_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_release_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.d.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_release_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
@@ -4606,6 +5311,11 @@ define void @cmpxchg_i64_release_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_release_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val release acquire
ret void
}
@@ -4674,6 +5384,11 @@ define void @cmpxchg_i64_acq_rel_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_acq_rel_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.d.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_acq_rel_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
@@ -4689,6 +5404,11 @@ define void @cmpxchg_i64_acq_rel_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_acq_rel_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acq_rel monotonic
ret void
}
@@ -4757,6 +5477,11 @@ define void @cmpxchg_i64_acq_rel_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_acq_rel_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.d.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_acq_rel_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
@@ -4772,6 +5497,11 @@ define void @cmpxchg_i64_acq_rel_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_acq_rel_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acq_rel acquire
ret void
}
@@ -4840,6 +5570,11 @@ define void @cmpxchg_i64_seq_cst_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_seq_cst_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.d.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_seq_cst_monotonic:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
@@ -4855,6 +5590,11 @@ define void @cmpxchg_i64_seq_cst_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwin
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_seq_cst_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst monotonic
ret void
}
@@ -4923,6 +5663,11 @@ define void @cmpxchg_i64_seq_cst_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_seq_cst_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.d.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_seq_cst_acquire:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
@@ -4938,6 +5683,11 @@ define void @cmpxchg_i64_seq_cst_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_seq_cst_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst acquire
ret void
}
@@ -5006,6 +5756,11 @@ define void @cmpxchg_i64_seq_cst_seq_cst(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-WMO-ZACAS-NEXT: amocas.d.aqrl a1, a2, (a0)
; RV64IA-WMO-ZACAS-NEXT: ret
;
+; RV64IA-WMO-ZABHA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amocas.d.aqrl a1, a2, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
; RV64IA-TSO-LABEL: cmpxchg_i64_seq_cst_seq_cst:
; RV64IA-TSO: # %bb.0:
; RV64IA-TSO-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
@@ -5021,6 +5776,13 @@ define void @cmpxchg_i64_seq_cst_seq_cst(ptr %ptr, i64 %cmp, i64 %val) nounwind
; RV64IA-TSO-ZACAS: # %bb.0:
; RV64IA-TSO-ZACAS-NEXT: amocas.d a1, a2, (a0)
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amocas.d a1, a2, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst seq_cst
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV64IA: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index 62206a6a2ece53..ee802507a02f3c 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -21,6 +21,15 @@
; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+experimental-zacas -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-TSO,RV64IA-TSO-ZACAS %s
+; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zabha -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO,RV64IA-WMO-ZABHA,RV64IA-WMO-ZABHA-NOZACAS %s
+; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+experimental-zabha -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO,RV64IA-TSO-ZABHA,RV64IA-TSO-ZABHA-NOZACAS %s
+; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zabha,+experimental-zacas -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO,RV64IA-WMO-ZABHA,RV64IA-WMO-ZABHA-ZACAS %s
+; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+experimental-zabha,+experimental-zacas -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO,RV64IA-TSO-ZABHA,RV64IA-TSO-ZABHA-ZACAS %s
+
define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_xchg_i8_monotonic:
; RV32I: # %bb.0:
@@ -62,25 +71,55 @@ define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_i8_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a4, (a2)
-; RV64IA-NEXT: mv a5, a1
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: and a5, a5, a3
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB0_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a4, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i8_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a3, 255
+; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-NOZACAS-NEXT: mv a5, a1
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB0_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_xchg_i8_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a3, 255
+; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-ZACAS-NEXT: mv a5, a1
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB0_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -146,45 +185,95 @@ define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_i8_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NEXT: mv a5, a1
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB1_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB1_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_i8_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: mv a5, a1
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB1_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i8_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB1_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i8_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB1_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i8_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB1_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 %b acquire
ret i8 %1
}
@@ -250,45 +339,95 @@ define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_i8_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-NEXT: mv a5, a1
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB2_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB2_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_i8_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: mv a5, a1
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB2_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i8_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB2_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i8_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB2_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i8_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB2_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 %b release
ret i8 %1
}
@@ -354,45 +493,95 @@ define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_i8_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NEXT: mv a5, a1
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB3_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB3_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_i8_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: mv a5, a1
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB3_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i8_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB3_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i8_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB3_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i8_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB3_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -438,25 +627,55 @@ define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_i8_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-NEXT: mv a5, a1
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: and a5, a5, a3
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB4_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a4, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i8_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a3, 255
+; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-NOZACAS-NEXT: mv a5, a1
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB4_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_xchg_i8_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a3, 255
+; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-ZACAS-NEXT: mv a5, a1
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB4_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -498,16 +717,37 @@ define i8 @atomicrmw_xchg_0_i8_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_0_i8_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: not a2, a2
-; RV64IA-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_0_i8_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a2, 255
+; RV64IA-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-NOZACAS-NEXT: not a2, a2
+; RV64IA-NOZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_xchg_0_i8_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a2, 255
+; RV64IA-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-ZACAS-NEXT: not a2, a2
+; RV64IA-ZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b a0, zero, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 monotonic
ret i8 %1
}
@@ -557,27 +797,59 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a2, 255
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: not a2, a2
-; RV64IA-WMO-NEXT: amoand.w.aq a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aq a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a2, 255
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: not a2, a2
-; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a2, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: not a2, a2
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.aq a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a2, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: not a2, a2
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aq a0, zero, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 acquire
ret i8 %1
}
@@ -627,27 +899,59 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a2, 255
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: not a2, a2
-; RV64IA-WMO-NEXT: amoand.w.rl a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.rl a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a2, 255
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: not a2, a2
-; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a2, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: not a2, a2
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.rl a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i8_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a2, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: not a2, a2
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b.rl a0, zero, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 release
ret i8 %1
}
@@ -697,27 +1001,59 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a2, 255
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: not a2, a2
-; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a2, 255
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: not a2, a2
-; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a2, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: not a2, a2
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a2, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: not a2, a2
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, zero, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 acq_rel
ret i8 %1
}
@@ -767,27 +1103,59 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_seq_cst:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a2, 255
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: not a2, a2
-; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_seq_cst:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a2, 255
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: not a2, a2
-; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a2, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: not a2, a2
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a2, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: not a2, a2
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, zero, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 seq_cst
ret i8 %1
}
@@ -825,15 +1193,37 @@ define i8 @atomicrmw_xchg_minus_1_i8_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_minus_1_i8_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a2, 255
+; RV64IA-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-NOZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a2, 255
+; RV64IA-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-ZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: li a1, -1
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: li a1, -1
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 monotonic
ret i8 %1
}
@@ -881,25 +1271,57 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a2, 255
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: amoor.w.aq a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aq a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a2, 255
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a2, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.aq a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a2, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: li a1, -1
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: li a1, -1
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 acquire
ret i8 %1
}
@@ -947,25 +1369,57 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a2, 255
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: amoor.w.rl a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.rl a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a2, 255
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a2, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.rl a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a2, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: li a1, -1
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: li a1, -1
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 release
ret i8 %1
}
@@ -1013,25 +1467,57 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a2, 255
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a2, 255
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a2, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a2, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: li a1, -1
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: li a1, -1
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 acq_rel
ret i8 %1
}
@@ -1079,25 +1565,57 @@ define i8 @atomicrmw_xchg_minus_1_i8_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a2, 255
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a2, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a2, 255
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a2, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a2, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a2, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: li a1, -1
+; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: li a1, -1
+; RV64IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 seq_cst
ret i8 %1
}
@@ -1143,25 +1661,55 @@ define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_add_i8_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a4, (a2)
-; RV64IA-NEXT: add a5, a4, a1
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: and a5, a5, a3
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB15_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a4, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_add_i8_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a3, 255
+; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-NOZACAS-NEXT: add a5, a4, a1
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB15_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_add_i8_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a3, 255
+; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-ZACAS-NEXT: add a5, a4, a1
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB15_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw add ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -1227,45 +1775,95 @@ define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_add_i8_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NEXT: add a5, a4, a1
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB16_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: add a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB16_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_add_i8_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: add a5, a4, a1
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB16_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_add_i8_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: add a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB16_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i8_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: add a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB16_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_add_i8_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: add a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB16_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw add ptr %a, i8 %b acquire
ret i8 %1
}
@@ -1331,45 +1929,95 @@ define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_add_i8_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-NEXT: add a5, a4, a1
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB17_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: add a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB17_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_add_i8_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: add a5, a4, a1
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB17_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_add_i8_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: add a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB17_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i8_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: add a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB17_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_add_i8_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: add a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB17_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoadd.b.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw add ptr %a, i8 %b release
ret i8 %1
}
@@ -1435,45 +2083,95 @@ define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_add_i8_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NEXT: add a5, a4, a1
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB18_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: add a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB18_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_add_i8_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: add a5, a4, a1
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB18_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_add_i8_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: add a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB18_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i8_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: add a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB18_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_add_i8_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: add a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB18_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw add ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -1519,25 +2217,55 @@ define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_add_i8_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-NEXT: add a5, a4, a1
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: and a5, a5, a3
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB19_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a4, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_add_i8_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a3, 255
+; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-NOZACAS-NEXT: add a5, a4, a1
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB19_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_add_i8_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a3, 255
+; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-ZACAS-NEXT: add a5, a4, a1
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB19_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw add ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -1583,25 +2311,57 @@ define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_sub_i8_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a4, (a2)
-; RV64IA-NEXT: sub a5, a4, a1
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: and a5, a5, a3
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB20_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a4, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i8_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a3, 255
+; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-NOZACAS-NEXT: sub a5, a4, a1
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB20_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_sub_i8_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a3, 255
+; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-ZACAS-NEXT: sub a5, a4, a1
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB20_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
+; RV64IA-WMO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
+; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw sub ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -1667,45 +2427,97 @@ define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_sub_i8_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NEXT: sub a5, a4, a1
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB21_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: sub a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB21_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i8_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: sub a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB21_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i8_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: sub a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB21_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_sub_i8_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: sub a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB21_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_sub_i8_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: sub a5, a4, a1
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB21_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
+; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
+; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw sub ptr %a, i8 %b acquire
ret i8 %1
}
@@ -1771,45 +2583,97 @@ define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_sub_i8_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-NEXT: sub a5, a4, a1
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB22_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: sub a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB22_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_sub_i8_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: sub a5, a4, a1
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB22_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i8_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: sub a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB22_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i8_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: sub a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB22_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_sub_i8_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: sub a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB22_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
+; RV64IA-WMO-ZABHA-NEXT: amoadd.b.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
+; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw sub ptr %a, i8 %b release
ret i8 %1
}
@@ -1875,45 +2739,97 @@ define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_sub_i8_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NEXT: sub a5, a4, a1
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB23_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: sub a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB23_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_sub_i8_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: sub a5, a4, a1
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB23_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i8_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: sub a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB23_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i8_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: sub a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB23_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_sub_i8_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: sub a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB23_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
+; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
+; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw sub ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -1959,25 +2875,57 @@ define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_sub_i8_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-NEXT: sub a5, a4, a1
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: and a5, a5, a3
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB24_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a4, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i8_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a3, 255
+; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-NOZACAS-NEXT: sub a5, a4, a1
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB24_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_sub_i8_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a3, 255
+; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-ZACAS-NEXT: sub a5, a4, a1
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB24_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
+; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
+; RV64IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw sub ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -2017,19 +2965,43 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i8_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: not a3, a3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: or a1, a3, a1
-; RV64IA-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_and_i8_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a3, 255
+; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-NOZACAS-NEXT: not a3, a3
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-NOZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_and_i8_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a3, 255
+; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-ZACAS-NEXT: not a3, a3
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-ZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoand.b a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -2083,33 +3055,71 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_and_i8_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: not a3, a3
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: or a1, a3, a1
-; RV64IA-WMO-NEXT: amoand.w.aq a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a3, a3
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aq a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_and_i8_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: not a3, a3
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: or a1, a3, a1
-; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i8_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a3, a3
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.aq a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i8_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoand.b.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b acquire
ret i8 %1
}
@@ -2163,33 +3173,71 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_and_i8_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: not a3, a3
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: or a1, a3, a1
-; RV64IA-WMO-NEXT: amoand.w.rl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a3, a3
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.rl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_and_i8_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: not a3, a3
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: or a1, a3, a1
-; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i8_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a3, a3
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.rl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i8_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoand.b.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b release
ret i8 %1
}
@@ -2243,33 +3291,71 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_and_i8_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: not a3, a3
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: or a1, a3, a1
-; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a3, a3
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_and_i8_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: not a3, a3
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: or a1, a3, a1
-; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i8_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a3, a3
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i8_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoand.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -2323,33 +3409,71 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_and_i8_seq_cst:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: not a3, a3
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: or a1, a3, a1
-; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_seq_cst:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a3, a3
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_and_i8_seq_cst:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: not a3, a3
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: or a1, a3, a1
-; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i8_seq_cst:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a3, a3
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_seq_cst:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i8_seq_cst:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: or a1, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoand.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw and ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -2396,26 +3520,119 @@ define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_nand_i8_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a4, (a2)
-; RV64IA-NEXT: and a5, a4, a1
-; RV64IA-NEXT: not a5, a5
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: and a5, a5, a3
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB30_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a4, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i8_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a3, 255
+; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-NOZACAS-NEXT: not a5, a5
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB30_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_nand_i8_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a3, 255
+; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-ZACAS-NEXT: and a5, a4, a1
+; RV64IA-ZACAS-NEXT: not a5, a5
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB30_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_monotonic:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB30_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_monotonic:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB30_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_monotonic:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB30_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB30_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_monotonic:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB30_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB30_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -2483,47 +3700,161 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_nand_i8_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NEXT: and a5, a4, a1
-; RV64IA-WMO-NEXT: not a5, a5
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB31_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB31_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_nand_i8_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: and a5, a4, a1
-; RV64IA-TSO-NEXT: not a5, a5
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB31_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i8_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB31_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i8_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB31_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_nand_i8_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB31_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_acquire:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB31_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_acquire:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB31_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_acquire:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB31_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.b.aq a0, a3, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB31_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_acquire:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB31_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB31_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i8 %b acquire
ret i8 %1
}
@@ -2591,47 +3922,161 @@ define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_nand_i8_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-NEXT: and a5, a4, a1
-; RV64IA-WMO-NEXT: not a5, a5
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB32_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB32_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_nand_i8_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: and a5, a4, a1
-; RV64IA-TSO-NEXT: not a5, a5
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB32_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i8_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB32_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i8_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB32_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_nand_i8_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB32_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_release:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB32_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_release:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB32_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_release:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB32_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.b.rl a0, a3, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB32_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_release:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB32_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB32_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i8 %b release
ret i8 %1
}
@@ -2699,47 +4144,161 @@ define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_nand_i8_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NEXT: and a5, a4, a1
-; RV64IA-WMO-NEXT: not a5, a5
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB33_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB33_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_nand_i8_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: and a5, a4, a1
-; RV64IA-TSO-NEXT: not a5, a5
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB33_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB33_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB33_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB33_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB33_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB33_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB33_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.b.aqrl a0, a3, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB33_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_acq_rel:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB33_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB33_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -2786,26 +4345,119 @@ define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_nand_i8_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-NEXT: and a5, a4, a1
-; RV64IA-NEXT: not a5, a5
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: and a5, a5, a3
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB34_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a4, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i8_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a3, 255
+; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-NOZACAS-NEXT: not a5, a5
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB34_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_nand_i8_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a3, 255
+; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-ZACAS-NEXT: and a5, a4, a1
+; RV64IA-ZACAS-NEXT: not a5, a5
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB34_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_seq_cst:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB34_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_seq_cst:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB34_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_seq_cst:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB34_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.b.aqrl a0, a3, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB34_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_seq_cst:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB34_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 56
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 56
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB34_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -2841,15 +4493,35 @@ define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i8_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_or_i8_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_or_i8_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoor.b a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -2895,25 +4567,55 @@ define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_or_i8_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoor.w.aq a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aq a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_or_i8_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i8_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.aq a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i8_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoor.b.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b acquire
ret i8 %1
}
@@ -2959,25 +4661,55 @@ define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_or_i8_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoor.w.rl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.rl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_or_i8_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i8_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.rl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i8_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoor.b.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b release
ret i8 %1
}
@@ -3023,25 +4755,55 @@ define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_or_i8_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_or_i8_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i8_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i8_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoor.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -3087,25 +4849,55 @@ define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_or_i8_seq_cst:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_seq_cst:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i8_seq_cst:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_or_i8_seq_cst:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_seq_cst:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i8_seq_cst:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoor.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw or ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -3141,15 +4933,35 @@ define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i8_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_xor_i8_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_xor_i8_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoxor.b a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -3195,25 +5007,55 @@ define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xor_i8_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoxor.w.aq a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.aq a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xor_i8_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i8_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoxor.w.aq a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i8_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoxor.b.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b acquire
ret i8 %1
}
@@ -3259,25 +5101,55 @@ define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xor_i8_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoxor.w.rl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.rl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xor_i8_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i8_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoxor.w.rl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i8_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoxor.b.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b release
ret i8 %1
}
@@ -3323,25 +5195,55 @@ define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xor_i8_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xor_i8_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoxor.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -3387,25 +5289,55 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xor_i8_seq_cst:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xor_i8_seq_cst:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoxor.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xor ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -3524,34 +5456,73 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_max_i8_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a3, a0, 24
-; RV64IA-NEXT: li a4, 255
-; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: slli a1, a1, 56
-; RV64IA-NEXT: srai a1, a1, 56
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: xori a3, a3, 56
-; RV64IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a5, (a2)
-; RV64IA-NEXT: and a7, a5, a4
-; RV64IA-NEXT: mv a6, a5
-; RV64IA-NEXT: sll a7, a7, a3
-; RV64IA-NEXT: sra a7, a7, a3
-; RV64IA-NEXT: bge a7, a1, .LBB45_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1
-; RV64IA-NEXT: xor a6, a5, a1
-; RV64IA-NEXT: and a6, a6, a4
-; RV64IA-NEXT: xor a6, a5, a6
-; RV64IA-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1
-; RV64IA-NEXT: sc.w a6, a6, (a2)
-; RV64IA-NEXT: bnez a6, .LBB45_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a5, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_max_i8_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-NOZACAS-NEXT: li a4, 255
+; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-NOZACAS-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-NOZACAS-NEXT: mv a6, a5
+; RV64IA-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-NOZACAS-NEXT: bge a7, a1, .LBB45_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-NOZACAS-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a6, .LBB45_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_max_i8_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-ZACAS-NEXT: li a4, 255
+; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-ZACAS-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-ZACAS-NEXT: mv a6, a5
+; RV64IA-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-ZACAS-NEXT: bge a7, a1, .LBB45_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-ZACAS-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-ZACAS-NEXT: bnez a6, .LBB45_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomax.b a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -3699,63 +5670,131 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_max_i8_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NEXT: li a4, 255
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: slli a1, a1, 56
-; RV64IA-WMO-NEXT: srai a1, a1, 56
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: xori a3, a3, 56
-; RV64IA-WMO-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a5, (a2)
-; RV64IA-WMO-NEXT: and a7, a5, a4
-; RV64IA-WMO-NEXT: mv a6, a5
-; RV64IA-WMO-NEXT: sll a7, a7, a3
-; RV64IA-WMO-NEXT: sra a7, a7, a3
-; RV64IA-WMO-NEXT: bge a7, a1, .LBB46_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
-; RV64IA-WMO-NEXT: xor a6, a5, a1
-; RV64IA-WMO-NEXT: and a6, a6, a4
-; RV64IA-WMO-NEXT: xor a6, a5, a6
-; RV64IA-WMO-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-WMO-NEXT: bnez a6, .LBB46_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NOZACAS-NEXT: li a4, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-WMO-NOZACAS-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a6, a5
+; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB46_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-WMO-NOZACAS-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB46_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_max_i8_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NEXT: li a4, 255
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: slli a1, a1, 56
-; RV64IA-TSO-NEXT: srai a1, a1, 56
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: xori a3, a3, 56
-; RV64IA-TSO-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-NEXT: and a7, a5, a4
-; RV64IA-TSO-NEXT: mv a6, a5
-; RV64IA-TSO-NEXT: sll a7, a7, a3
-; RV64IA-TSO-NEXT: sra a7, a7, a3
-; RV64IA-TSO-NEXT: bge a7, a1, .LBB46_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
-; RV64IA-TSO-NEXT: xor a6, a5, a1
-; RV64IA-TSO-NEXT: and a6, a6, a4
-; RV64IA-TSO-NEXT: xor a6, a5, a6
-; RV64IA-TSO-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NEXT: bnez a6, .LBB46_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_max_i8_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NOZACAS-NEXT: li a4, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-TSO-NOZACAS-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a6, a5
+; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB46_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-TSO-NOZACAS-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB46_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i8_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-ZACAS-NEXT: li a4, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-WMO-ZACAS-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a6, a5
+; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB46_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-WMO-ZACAS-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB46_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_max_i8_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-ZACAS-NEXT: li a4, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-TSO-ZACAS-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a6, a5
+; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB46_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-TSO-ZACAS-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB46_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomax.b.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b acquire
ret i8 %1
}
@@ -3903,63 +5942,131 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_max_i8_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NEXT: li a4, 255
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: slli a1, a1, 56
-; RV64IA-WMO-NEXT: srai a1, a1, 56
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: xori a3, a3, 56
-; RV64IA-WMO-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a5, (a2)
-; RV64IA-WMO-NEXT: and a7, a5, a4
-; RV64IA-WMO-NEXT: mv a6, a5
-; RV64IA-WMO-NEXT: sll a7, a7, a3
-; RV64IA-WMO-NEXT: sra a7, a7, a3
-; RV64IA-WMO-NEXT: bge a7, a1, .LBB47_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
-; RV64IA-WMO-NEXT: xor a6, a5, a1
-; RV64IA-WMO-NEXT: and a6, a6, a4
-; RV64IA-WMO-NEXT: xor a6, a5, a6
-; RV64IA-WMO-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NEXT: bnez a6, .LBB47_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NOZACAS-NEXT: li a4, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-WMO-NOZACAS-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a6, a5
+; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB47_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-WMO-NOZACAS-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB47_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_max_i8_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NEXT: li a4, 255
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: slli a1, a1, 56
-; RV64IA-TSO-NEXT: srai a1, a1, 56
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: xori a3, a3, 56
-; RV64IA-TSO-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-NEXT: and a7, a5, a4
-; RV64IA-TSO-NEXT: mv a6, a5
-; RV64IA-TSO-NEXT: sll a7, a7, a3
-; RV64IA-TSO-NEXT: sra a7, a7, a3
-; RV64IA-TSO-NEXT: bge a7, a1, .LBB47_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
-; RV64IA-TSO-NEXT: xor a6, a5, a1
-; RV64IA-TSO-NEXT: and a6, a6, a4
-; RV64IA-TSO-NEXT: xor a6, a5, a6
-; RV64IA-TSO-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NEXT: bnez a6, .LBB47_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_max_i8_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NOZACAS-NEXT: li a4, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-TSO-NOZACAS-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a6, a5
+; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB47_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-TSO-NOZACAS-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB47_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i8_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-ZACAS-NEXT: li a4, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-WMO-ZACAS-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a6, a5
+; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB47_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-WMO-ZACAS-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB47_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_max_i8_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-ZACAS-NEXT: li a4, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-TSO-ZACAS-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a6, a5
+; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB47_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-TSO-ZACAS-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB47_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomax.b.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b release
ret i8 %1
}
@@ -4107,63 +6214,131 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_max_i8_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NEXT: li a4, 255
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: slli a1, a1, 56
-; RV64IA-WMO-NEXT: srai a1, a1, 56
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: xori a3, a3, 56
-; RV64IA-WMO-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a5, (a2)
-; RV64IA-WMO-NEXT: and a7, a5, a4
-; RV64IA-WMO-NEXT: mv a6, a5
-; RV64IA-WMO-NEXT: sll a7, a7, a3
-; RV64IA-WMO-NEXT: sra a7, a7, a3
-; RV64IA-WMO-NEXT: bge a7, a1, .LBB48_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
-; RV64IA-WMO-NEXT: xor a6, a5, a1
-; RV64IA-WMO-NEXT: and a6, a6, a4
-; RV64IA-WMO-NEXT: xor a6, a5, a6
-; RV64IA-WMO-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NEXT: bnez a6, .LBB48_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NOZACAS-NEXT: li a4, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-WMO-NOZACAS-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a6, a5
+; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB48_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-WMO-NOZACAS-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB48_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_max_i8_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NEXT: li a4, 255
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: slli a1, a1, 56
-; RV64IA-TSO-NEXT: srai a1, a1, 56
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: xori a3, a3, 56
-; RV64IA-TSO-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-NEXT: and a7, a5, a4
-; RV64IA-TSO-NEXT: mv a6, a5
-; RV64IA-TSO-NEXT: sll a7, a7, a3
-; RV64IA-TSO-NEXT: sra a7, a7, a3
-; RV64IA-TSO-NEXT: bge a7, a1, .LBB48_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
-; RV64IA-TSO-NEXT: xor a6, a5, a1
-; RV64IA-TSO-NEXT: and a6, a6, a4
-; RV64IA-TSO-NEXT: xor a6, a5, a6
-; RV64IA-TSO-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NEXT: bnez a6, .LBB48_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_max_i8_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NOZACAS-NEXT: li a4, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-TSO-NOZACAS-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a6, a5
+; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB48_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-TSO-NOZACAS-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB48_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i8_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-ZACAS-NEXT: li a4, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-WMO-ZACAS-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a6, a5
+; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB48_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-WMO-ZACAS-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB48_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_max_i8_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-ZACAS-NEXT: li a4, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-TSO-ZACAS-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a6, a5
+; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB48_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-TSO-ZACAS-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB48_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomax.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -4282,34 +6457,73 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_max_i8_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a3, a0, 24
-; RV64IA-NEXT: li a4, 255
-; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: slli a1, a1, 56
-; RV64IA-NEXT: srai a1, a1, 56
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: xori a3, a3, 56
-; RV64IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a5, (a2)
-; RV64IA-NEXT: and a7, a5, a4
-; RV64IA-NEXT: mv a6, a5
-; RV64IA-NEXT: sll a7, a7, a3
-; RV64IA-NEXT: sra a7, a7, a3
-; RV64IA-NEXT: bge a7, a1, .LBB49_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
-; RV64IA-NEXT: xor a6, a5, a1
-; RV64IA-NEXT: and a6, a6, a4
-; RV64IA-NEXT: xor a6, a5, a6
-; RV64IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1
-; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-NEXT: bnez a6, .LBB49_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a5, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_max_i8_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-NOZACAS-NEXT: li a4, 255
+; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-NOZACAS-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a5, (a2)
+; RV64IA-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-NOZACAS-NEXT: mv a6, a5
+; RV64IA-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-NOZACAS-NEXT: bge a7, a1, .LBB49_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-NOZACAS-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a6, .LBB49_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_max_i8_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-ZACAS-NEXT: li a4, 255
+; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-ZACAS-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a5, (a2)
+; RV64IA-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-ZACAS-NEXT: mv a6, a5
+; RV64IA-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-ZACAS-NEXT: bge a7, a1, .LBB49_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-ZACAS-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-ZACAS-NEXT: bnez a6, .LBB49_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomax.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -4428,34 +6642,73 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_min_i8_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a3, a0, 24
-; RV64IA-NEXT: li a4, 255
-; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: slli a1, a1, 56
-; RV64IA-NEXT: srai a1, a1, 56
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: xori a3, a3, 56
-; RV64IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a5, (a2)
-; RV64IA-NEXT: and a7, a5, a4
-; RV64IA-NEXT: mv a6, a5
-; RV64IA-NEXT: sll a7, a7, a3
-; RV64IA-NEXT: sra a7, a7, a3
-; RV64IA-NEXT: bge a1, a7, .LBB50_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1
-; RV64IA-NEXT: xor a6, a5, a1
-; RV64IA-NEXT: and a6, a6, a4
-; RV64IA-NEXT: xor a6, a5, a6
-; RV64IA-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1
-; RV64IA-NEXT: sc.w a6, a6, (a2)
-; RV64IA-NEXT: bnez a6, .LBB50_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a5, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_min_i8_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-NOZACAS-NEXT: li a4, 255
+; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-NOZACAS-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-NOZACAS-NEXT: mv a6, a5
+; RV64IA-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-NOZACAS-NEXT: bge a1, a7, .LBB50_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-NOZACAS-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a6, .LBB50_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_min_i8_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-ZACAS-NEXT: li a4, 255
+; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-ZACAS-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-ZACAS-NEXT: mv a6, a5
+; RV64IA-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-ZACAS-NEXT: bge a1, a7, .LBB50_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-ZACAS-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-ZACAS-NEXT: bnez a6, .LBB50_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomin.b a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -4603,63 +6856,131 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_min_i8_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NEXT: li a4, 255
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: slli a1, a1, 56
-; RV64IA-WMO-NEXT: srai a1, a1, 56
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: xori a3, a3, 56
-; RV64IA-WMO-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a5, (a2)
-; RV64IA-WMO-NEXT: and a7, a5, a4
-; RV64IA-WMO-NEXT: mv a6, a5
-; RV64IA-WMO-NEXT: sll a7, a7, a3
-; RV64IA-WMO-NEXT: sra a7, a7, a3
-; RV64IA-WMO-NEXT: bge a1, a7, .LBB51_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
-; RV64IA-WMO-NEXT: xor a6, a5, a1
-; RV64IA-WMO-NEXT: and a6, a6, a4
-; RV64IA-WMO-NEXT: xor a6, a5, a6
-; RV64IA-WMO-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-WMO-NEXT: bnez a6, .LBB51_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NOZACAS-NEXT: li a4, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-WMO-NOZACAS-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a6, a5
+; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB51_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-WMO-NOZACAS-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB51_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_min_i8_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NEXT: li a4, 255
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: slli a1, a1, 56
-; RV64IA-TSO-NEXT: srai a1, a1, 56
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: xori a3, a3, 56
-; RV64IA-TSO-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-NEXT: and a7, a5, a4
-; RV64IA-TSO-NEXT: mv a6, a5
-; RV64IA-TSO-NEXT: sll a7, a7, a3
-; RV64IA-TSO-NEXT: sra a7, a7, a3
-; RV64IA-TSO-NEXT: bge a1, a7, .LBB51_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
-; RV64IA-TSO-NEXT: xor a6, a5, a1
-; RV64IA-TSO-NEXT: and a6, a6, a4
-; RV64IA-TSO-NEXT: xor a6, a5, a6
-; RV64IA-TSO-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NEXT: bnez a6, .LBB51_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_min_i8_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NOZACAS-NEXT: li a4, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-TSO-NOZACAS-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a6, a5
+; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB51_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-TSO-NOZACAS-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB51_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i8_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-ZACAS-NEXT: li a4, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-WMO-ZACAS-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a6, a5
+; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB51_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-WMO-ZACAS-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB51_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_min_i8_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-ZACAS-NEXT: li a4, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-TSO-ZACAS-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a6, a5
+; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB51_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-TSO-ZACAS-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB51_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomin.b.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b acquire
ret i8 %1
}
@@ -4807,63 +7128,131 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_min_i8_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NEXT: li a4, 255
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: slli a1, a1, 56
-; RV64IA-WMO-NEXT: srai a1, a1, 56
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: xori a3, a3, 56
-; RV64IA-WMO-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a5, (a2)
-; RV64IA-WMO-NEXT: and a7, a5, a4
-; RV64IA-WMO-NEXT: mv a6, a5
-; RV64IA-WMO-NEXT: sll a7, a7, a3
-; RV64IA-WMO-NEXT: sra a7, a7, a3
-; RV64IA-WMO-NEXT: bge a1, a7, .LBB52_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
-; RV64IA-WMO-NEXT: xor a6, a5, a1
-; RV64IA-WMO-NEXT: and a6, a6, a4
-; RV64IA-WMO-NEXT: xor a6, a5, a6
-; RV64IA-WMO-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NEXT: bnez a6, .LBB52_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NOZACAS-NEXT: li a4, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-WMO-NOZACAS-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a6, a5
+; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB52_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-WMO-NOZACAS-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB52_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_min_i8_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NEXT: li a4, 255
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: slli a1, a1, 56
-; RV64IA-TSO-NEXT: srai a1, a1, 56
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: xori a3, a3, 56
-; RV64IA-TSO-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-NEXT: and a7, a5, a4
-; RV64IA-TSO-NEXT: mv a6, a5
-; RV64IA-TSO-NEXT: sll a7, a7, a3
-; RV64IA-TSO-NEXT: sra a7, a7, a3
-; RV64IA-TSO-NEXT: bge a1, a7, .LBB52_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
-; RV64IA-TSO-NEXT: xor a6, a5, a1
-; RV64IA-TSO-NEXT: and a6, a6, a4
-; RV64IA-TSO-NEXT: xor a6, a5, a6
-; RV64IA-TSO-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NEXT: bnez a6, .LBB52_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_min_i8_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NOZACAS-NEXT: li a4, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-TSO-NOZACAS-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a6, a5
+; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB52_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-TSO-NOZACAS-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB52_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i8_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-ZACAS-NEXT: li a4, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-WMO-ZACAS-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a6, a5
+; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB52_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-WMO-ZACAS-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB52_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_min_i8_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-ZACAS-NEXT: li a4, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-TSO-ZACAS-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a6, a5
+; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB52_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-TSO-ZACAS-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB52_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomin.b.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b release
ret i8 %1
}
@@ -5011,63 +7400,131 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_min_i8_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NEXT: li a4, 255
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: slli a1, a1, 56
-; RV64IA-WMO-NEXT: srai a1, a1, 56
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: xori a3, a3, 56
-; RV64IA-WMO-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a5, (a2)
-; RV64IA-WMO-NEXT: and a7, a5, a4
-; RV64IA-WMO-NEXT: mv a6, a5
-; RV64IA-WMO-NEXT: sll a7, a7, a3
-; RV64IA-WMO-NEXT: sra a7, a7, a3
-; RV64IA-WMO-NEXT: bge a1, a7, .LBB53_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
-; RV64IA-WMO-NEXT: xor a6, a5, a1
-; RV64IA-WMO-NEXT: and a6, a6, a4
-; RV64IA-WMO-NEXT: xor a6, a5, a6
-; RV64IA-WMO-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NEXT: bnez a6, .LBB53_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a5, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NOZACAS-NEXT: li a4, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-WMO-NOZACAS-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a6, a5
+; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB53_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-WMO-NOZACAS-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB53_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_min_i8_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NEXT: li a4, 255
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: slli a1, a1, 56
-; RV64IA-TSO-NEXT: srai a1, a1, 56
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: xori a3, a3, 56
-; RV64IA-TSO-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a5, (a2)
-; RV64IA-TSO-NEXT: and a7, a5, a4
-; RV64IA-TSO-NEXT: mv a6, a5
-; RV64IA-TSO-NEXT: sll a7, a7, a3
-; RV64IA-TSO-NEXT: sra a7, a7, a3
-; RV64IA-TSO-NEXT: bge a1, a7, .LBB53_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
-; RV64IA-TSO-NEXT: xor a6, a5, a1
-; RV64IA-TSO-NEXT: and a6, a6, a4
-; RV64IA-TSO-NEXT: xor a6, a5, a6
-; RV64IA-TSO-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NEXT: bnez a6, .LBB53_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a5, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_min_i8_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NOZACAS-NEXT: li a4, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-TSO-NOZACAS-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a6, a5
+; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB53_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-TSO-NOZACAS-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB53_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i8_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-ZACAS-NEXT: li a4, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-WMO-ZACAS-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a6, a5
+; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB53_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-WMO-ZACAS-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB53_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_min_i8_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-ZACAS-NEXT: li a4, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-TSO-ZACAS-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a6, a5
+; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB53_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-TSO-ZACAS-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB53_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomin.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -5186,34 +7643,73 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_min_i8_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a3, a0, 24
-; RV64IA-NEXT: li a4, 255
-; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: slli a1, a1, 56
-; RV64IA-NEXT: srai a1, a1, 56
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: xori a3, a3, 56
-; RV64IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a5, (a2)
-; RV64IA-NEXT: and a7, a5, a4
-; RV64IA-NEXT: mv a6, a5
-; RV64IA-NEXT: sll a7, a7, a3
-; RV64IA-NEXT: sra a7, a7, a3
-; RV64IA-NEXT: bge a1, a7, .LBB54_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1
-; RV64IA-NEXT: xor a6, a5, a1
-; RV64IA-NEXT: and a6, a6, a4
-; RV64IA-NEXT: xor a6, a5, a6
-; RV64IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1
-; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-NEXT: bnez a6, .LBB54_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a5, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_min_i8_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-NOZACAS-NEXT: li a4, 255
+; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-NOZACAS-NEXT: slli a1, a1, 56
+; RV64IA-NOZACAS-NEXT: srai a1, a1, 56
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: xori a3, a3, 56
+; RV64IA-NOZACAS-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a5, (a2)
+; RV64IA-NOZACAS-NEXT: and a7, a5, a4
+; RV64IA-NOZACAS-NEXT: mv a6, a5
+; RV64IA-NOZACAS-NEXT: sll a7, a7, a3
+; RV64IA-NOZACAS-NEXT: sra a7, a7, a3
+; RV64IA-NOZACAS-NEXT: bge a1, a7, .LBB54_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a6, a5, a1
+; RV64IA-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-NOZACAS-NEXT: xor a6, a5, a6
+; RV64IA-NOZACAS-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a6, .LBB54_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_min_i8_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-ZACAS-NEXT: li a4, 255
+; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-ZACAS-NEXT: slli a1, a1, 56
+; RV64IA-ZACAS-NEXT: srai a1, a1, 56
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: xori a3, a3, 56
+; RV64IA-ZACAS-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a5, (a2)
+; RV64IA-ZACAS-NEXT: and a7, a5, a4
+; RV64IA-ZACAS-NEXT: mv a6, a5
+; RV64IA-ZACAS-NEXT: sll a7, a7, a3
+; RV64IA-ZACAS-NEXT: sra a7, a7, a3
+; RV64IA-ZACAS-NEXT: bge a1, a7, .LBB54_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a6, a5, a1
+; RV64IA-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-ZACAS-NEXT: xor a6, a5, a6
+; RV64IA-ZACAS-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-ZACAS-NEXT: bnez a6, .LBB54_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a5, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomin.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -5323,29 +7819,63 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umax_i8_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a4, (a2)
-; RV64IA-NEXT: and a6, a4, a3
-; RV64IA-NEXT: mv a5, a4
-; RV64IA-NEXT: bgeu a6, a1, .LBB55_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB55_1 Depth=1
-; RV64IA-NEXT: xor a5, a4, a1
-; RV64IA-NEXT: and a5, a5, a3
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: .LBB55_3: # in Loop: Header=BB55_1 Depth=1
-; RV64IA-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB55_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a4, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i8_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a3, 255
+; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-NOZACAS-NEXT: mv a5, a4
+; RV64IA-NOZACAS-NEXT: bgeu a6, a1, .LBB55_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB55_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: .LBB55_3: # in Loop: Header=BB55_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB55_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_umax_i8_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a3, 255
+; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-ZACAS-NEXT: mv a5, a4
+; RV64IA-ZACAS-NEXT: bgeu a6, a1, .LBB55_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB55_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: .LBB55_3: # in Loop: Header=BB55_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB55_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomaxu.b a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -5479,53 +8009,111 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_umax_i8_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NEXT: and a6, a4, a3
-; RV64IA-WMO-NEXT: mv a5, a4
-; RV64IA-WMO-NEXT: bgeu a6, a1, .LBB56_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a4, a1
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB56_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB56_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB56_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_umax_i8_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: and a6, a4, a3
-; RV64IA-TSO-NEXT: mv a5, a4
-; RV64IA-TSO-NEXT: bgeu a6, a1, .LBB56_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a4, a1
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB56_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i8_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB56_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB56_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i8_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a4
+; RV64IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB56_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB56_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umax_i8_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a4
+; RV64IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB56_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB56_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomaxu.b.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b acquire
ret i8 %1
}
@@ -5659,53 +8247,111 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_umax_i8_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-NEXT: and a6, a4, a3
-; RV64IA-WMO-NEXT: mv a5, a4
-; RV64IA-WMO-NEXT: bgeu a6, a1, .LBB57_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a4, a1
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB57_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB57_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB57_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i8_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB57_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB57_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i8_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a4
+; RV64IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB57_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB57_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umax_i8_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a4
+; RV64IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB57_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB57_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomaxu.b.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_umax_i8_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: and a6, a4, a3
-; RV64IA-TSO-NEXT: mv a5, a4
-; RV64IA-TSO-NEXT: bgeu a6, a1, .LBB57_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a4, a1
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB57_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b release
ret i8 %1
}
@@ -5839,53 +8485,111 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_umax_i8_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NEXT: and a6, a4, a3
-; RV64IA-WMO-NEXT: mv a5, a4
-; RV64IA-WMO-NEXT: bgeu a6, a1, .LBB58_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a4, a1
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB58_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB58_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB58_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_umax_i8_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: and a6, a4, a3
-; RV64IA-TSO-NEXT: mv a5, a4
-; RV64IA-TSO-NEXT: bgeu a6, a1, .LBB58_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a4, a1
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB58_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i8_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB58_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB58_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i8_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a4
+; RV64IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB58_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB58_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umax_i8_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a4
+; RV64IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB58_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB58_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomaxu.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -5995,29 +8699,63 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umax_i8_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-NEXT: and a6, a4, a3
-; RV64IA-NEXT: mv a5, a4
-; RV64IA-NEXT: bgeu a6, a1, .LBB59_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB59_1 Depth=1
-; RV64IA-NEXT: xor a5, a4, a1
-; RV64IA-NEXT: and a5, a5, a3
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: .LBB59_3: # in Loop: Header=BB59_1 Depth=1
-; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB59_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a4, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i8_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a3, 255
+; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-NOZACAS-NEXT: mv a5, a4
+; RV64IA-NOZACAS-NEXT: bgeu a6, a1, .LBB59_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB59_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: .LBB59_3: # in Loop: Header=BB59_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB59_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_umax_i8_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a3, 255
+; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-ZACAS-NEXT: mv a5, a4
+; RV64IA-ZACAS-NEXT: bgeu a6, a1, .LBB59_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB59_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: .LBB59_3: # in Loop: Header=BB59_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB59_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomaxu.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -6127,29 +8865,63 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umin_i8_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a4, (a2)
-; RV64IA-NEXT: and a6, a4, a3
-; RV64IA-NEXT: mv a5, a4
-; RV64IA-NEXT: bgeu a1, a6, .LBB60_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB60_1 Depth=1
-; RV64IA-NEXT: xor a5, a4, a1
-; RV64IA-NEXT: and a5, a5, a3
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: .LBB60_3: # in Loop: Header=BB60_1 Depth=1
-; RV64IA-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB60_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a4, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i8_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a3, 255
+; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-NOZACAS-NEXT: mv a5, a4
+; RV64IA-NOZACAS-NEXT: bgeu a1, a6, .LBB60_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB60_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: .LBB60_3: # in Loop: Header=BB60_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB60_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_umin_i8_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a3, 255
+; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-ZACAS-NEXT: mv a5, a4
+; RV64IA-ZACAS-NEXT: bgeu a1, a6, .LBB60_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB60_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: .LBB60_3: # in Loop: Header=BB60_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB60_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amominu.b a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b monotonic
ret i8 %1
}
@@ -6283,53 +9055,111 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_umin_i8_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NEXT: and a6, a4, a3
-; RV64IA-WMO-NEXT: mv a5, a4
-; RV64IA-WMO-NEXT: bgeu a1, a6, .LBB61_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a4, a1
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB61_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB61_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB61_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_umin_i8_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: and a6, a4, a3
-; RV64IA-TSO-NEXT: mv a5, a4
-; RV64IA-TSO-NEXT: bgeu a1, a6, .LBB61_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a4, a1
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB61_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i8_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB61_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB61_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i8_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a4
+; RV64IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB61_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB61_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umin_i8_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a4
+; RV64IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB61_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB61_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amominu.b.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b acquire
ret i8 %1
}
@@ -6463,53 +9293,111 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_umin_i8_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a4, (a2)
-; RV64IA-WMO-NEXT: and a6, a4, a3
-; RV64IA-WMO-NEXT: mv a5, a4
-; RV64IA-WMO-NEXT: bgeu a1, a6, .LBB62_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a4, a1
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB62_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB62_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB62_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_umin_i8_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: and a6, a4, a3
-; RV64IA-TSO-NEXT: mv a5, a4
-; RV64IA-TSO-NEXT: bgeu a1, a6, .LBB62_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a4, a1
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB62_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i8_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB62_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB62_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i8_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a4
+; RV64IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB62_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB62_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umin_i8_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a4
+; RV64IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB62_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB62_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amominu.b.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b release
ret i8 %1
}
@@ -6643,53 +9531,111 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_umin_i8_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: li a3, 255
-; RV64IA-WMO-NEXT: sllw a3, a3, a0
-; RV64IA-WMO-NEXT: andi a1, a1, 255
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a4, (a2)
-; RV64IA-WMO-NEXT: and a6, a4, a3
-; RV64IA-WMO-NEXT: mv a5, a4
-; RV64IA-WMO-NEXT: bgeu a1, a6, .LBB63_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a4, a1
-; RV64IA-WMO-NEXT: and a5, a5, a3
-; RV64IA-WMO-NEXT: xor a5, a4, a5
-; RV64IA-WMO-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB63_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a4, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: li a3, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB63_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-NOZACAS-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB63_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_umin_i8_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: li a3, 255
-; RV64IA-TSO-NEXT: sllw a3, a3, a0
-; RV64IA-TSO-NEXT: andi a1, a1, 255
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a4, (a2)
-; RV64IA-TSO-NEXT: and a6, a4, a3
-; RV64IA-TSO-NEXT: mv a5, a4
-; RV64IA-TSO-NEXT: bgeu a1, a6, .LBB63_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a4, a1
-; RV64IA-TSO-NEXT: and a5, a5, a3
-; RV64IA-TSO-NEXT: xor a5, a4, a5
-; RV64IA-TSO-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB63_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a4, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i8_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: li a3, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB63_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-NOZACAS-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB63_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i8_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: li a3, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a4
+; RV64IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB63_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-WMO-ZACAS-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB63_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umin_i8_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: li a3, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a4, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a4
+; RV64IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB63_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-TSO-ZACAS-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB63_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amominu.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b acq_rel
ret i8 %1
}
@@ -6799,29 +9745,63 @@ define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umin_i8_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a3, 255
-; RV64IA-NEXT: sllw a3, a3, a0
-; RV64IA-NEXT: andi a1, a1, 255
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a4, (a2)
-; RV64IA-NEXT: and a6, a4, a3
-; RV64IA-NEXT: mv a5, a4
-; RV64IA-NEXT: bgeu a1, a6, .LBB64_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB64_1 Depth=1
-; RV64IA-NEXT: xor a5, a4, a1
-; RV64IA-NEXT: and a5, a5, a3
-; RV64IA-NEXT: xor a5, a4, a5
-; RV64IA-NEXT: .LBB64_3: # in Loop: Header=BB64_1 Depth=1
-; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB64_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a4, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i8_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: li a3, 255
+; RV64IA-NOZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-NOZACAS-NEXT: andi a1, a1, 255
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-NOZACAS-NEXT: and a6, a4, a3
+; RV64IA-NOZACAS-NEXT: mv a5, a4
+; RV64IA-NOZACAS-NEXT: bgeu a1, a6, .LBB64_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB64_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a1
+; RV64IA-NOZACAS-NEXT: and a5, a5, a3
+; RV64IA-NOZACAS-NEXT: xor a5, a4, a5
+; RV64IA-NOZACAS-NEXT: .LBB64_3: # in Loop: Header=BB64_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB64_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_umin_i8_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: li a3, 255
+; RV64IA-ZACAS-NEXT: sllw a3, a3, a0
+; RV64IA-ZACAS-NEXT: andi a1, a1, 255
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a2)
+; RV64IA-ZACAS-NEXT: and a6, a4, a3
+; RV64IA-ZACAS-NEXT: mv a5, a4
+; RV64IA-ZACAS-NEXT: bgeu a1, a6, .LBB64_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB64_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a5, a4, a1
+; RV64IA-ZACAS-NEXT: and a5, a5, a3
+; RV64IA-ZACAS-NEXT: xor a5, a4, a5
+; RV64IA-ZACAS-NEXT: .LBB64_3: # in Loop: Header=BB64_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB64_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a4, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amominu.b.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b seq_cst
ret i8 %1
}
@@ -6868,26 +9848,57 @@ define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_i16_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addi a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a3, (a2)
-; RV64IA-NEXT: mv a5, a1
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB65_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i16_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-NOZACAS-NEXT: mv a5, a1
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB65_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_xchg_i16_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a3, 16
+; RV64IA-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-ZACAS-NEXT: mv a5, a1
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB65_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -6955,47 +9966,99 @@ define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_i16_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: mv a5, a1
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB66_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB66_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_i16_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: mv a5, a1
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB66_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i16_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB66_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i16_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB66_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i16_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB66_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 %b acquire
ret i16 %1
}
@@ -7063,47 +10126,99 @@ define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_i16_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NEXT: mv a5, a1
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB67_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB67_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_i16_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: mv a5, a1
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB67_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i16_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB67_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i16_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB67_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i16_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB67_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 %b release
ret i16 %1
}
@@ -7171,47 +10286,99 @@ define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_i16_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: mv a5, a1
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB68_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB68_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_i16_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: mv a5, a1
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB68_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i16_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB68_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i16_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB68_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i16_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB68_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -7258,26 +10425,57 @@ define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_i16_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addi a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NEXT: mv a5, a1
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB69_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_i16_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NOZACAS-NEXT: mv a5, a1
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB69_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_xchg_i16_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a3, 16
+; RV64IA-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-ZACAS-NEXT: mv a5, a1
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB69_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -7320,17 +10518,39 @@ define i16 @atomicrmw_xchg_0_i16_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_0_i16_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a2, 16
-; RV64IA-NEXT: addi a2, a2, -1
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: not a2, a2
-; RV64IA-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_0_i16_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a2, 16
+; RV64IA-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-NOZACAS-NEXT: not a2, a2
+; RV64IA-NOZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_xchg_0_i16_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a2, 16
+; RV64IA-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-ZACAS-NEXT: not a2, a2
+; RV64IA-ZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h a0, zero, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 0 monotonic
ret i16 %1
}
@@ -7382,29 +10602,63 @@ define i16 @atomicrmw_xchg_0_i16_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i16_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a2, 16
-; RV64IA-WMO-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: not a2, a2
-; RV64IA-WMO-NEXT: amoand.w.aq a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aq a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i16_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a2, 16
-; RV64IA-TSO-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: not a2, a2
-; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: not a2, a2
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.aq a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i16_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: not a2, a2
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aq a0, zero, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 0 acquire
ret i16 %1
}
@@ -7456,29 +10710,63 @@ define i16 @atomicrmw_xchg_0_i16_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i16_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a2, 16
-; RV64IA-WMO-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: not a2, a2
-; RV64IA-WMO-NEXT: amoand.w.rl a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.rl a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i16_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a2, 16
-; RV64IA-TSO-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: not a2, a2
-; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: not a2, a2
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.rl a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i16_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: not a2, a2
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h.rl a0, zero, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 0 release
ret i16 %1
}
@@ -7530,29 +10818,63 @@ define i16 @atomicrmw_xchg_0_i16_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i16_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a2, 16
-; RV64IA-WMO-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: not a2, a2
-; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i16_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a2, 16
-; RV64IA-TSO-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: not a2, a2
-; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: not a2, a2
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: not a2, a2
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, zero, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 0 acq_rel
ret i16 %1
}
@@ -7604,29 +10926,63 @@ define i16 @atomicrmw_xchg_0_i16_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i16_seq_cst:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a2, 16
-; RV64IA-WMO-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: not a2, a2
-; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a2, a2
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i16_seq_cst:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a2, 16
-; RV64IA-TSO-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: not a2, a2
-; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a2, a2
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: not a2, a2
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: not a2, a2
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, zero, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 0 seq_cst
ret i16 %1
}
@@ -7667,16 +11023,39 @@ define i16 @atomicrmw_xchg_minus_1_i16_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_minus_1_i16_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a2, 16
-; RV64IA-NEXT: addi a2, a2, -1
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a2, 16
+; RV64IA-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-NOZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a2, 16
+; RV64IA-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-ZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: li a1, -1
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: li a1, -1
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 -1 monotonic
ret i16 %1
}
@@ -7728,27 +11107,61 @@ define i16 @atomicrmw_xchg_minus_1_i16_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a2, 16
-; RV64IA-WMO-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: amoor.w.aq a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aq a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.aq a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a2, 16
-; RV64IA-TSO-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: li a1, -1
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: li a1, -1
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 -1 acquire
ret i16 %1
}
@@ -7800,27 +11213,61 @@ define i16 @atomicrmw_xchg_minus_1_i16_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a2, 16
-; RV64IA-WMO-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: amoor.w.rl a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.rl a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a2, 16
-; RV64IA-TSO-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.rl a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: li a1, -1
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: li a1, -1
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 -1 release
ret i16 %1
}
@@ -7872,27 +11319,61 @@ define i16 @atomicrmw_xchg_minus_1_i16_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a2, 16
-; RV64IA-WMO-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a2, 16
-; RV64IA-TSO-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: li a1, -1
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: li a1, -1
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 -1 acq_rel
ret i16 %1
}
@@ -7944,27 +11425,61 @@ define i16 @atomicrmw_xchg_minus_1_i16_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a1, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a2, 16
-; RV64IA-WMO-NEXT: addi a2, a2, -1
-; RV64IA-WMO-NEXT: sllw a2, a2, a0
-; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a1, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a2, 16
-; RV64IA-TSO-NEXT: addi a2, a2, -1
-; RV64IA-TSO-NEXT: sllw a2, a2, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a2, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a1, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a2, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a2, a2, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: li a1, -1
+; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: li a1, -1
+; RV64IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xchg ptr %a, i16 -1 seq_cst
ret i16 %1
}
@@ -8011,26 +11526,57 @@ define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_add_i16_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addi a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a3, (a2)
-; RV64IA-NEXT: add a5, a3, a1
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB80_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_add_i16_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-NOZACAS-NEXT: add a5, a3, a1
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB80_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_add_i16_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a3, 16
+; RV64IA-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-ZACAS-NEXT: add a5, a3, a1
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB80_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw add ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -8098,47 +11644,99 @@ define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_add_i16_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: add a5, a3, a1
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB81_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: add a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB81_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_add_i16_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: add a5, a3, a1
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB81_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_add_i16_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: add a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB81_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i16_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: add a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB81_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_add_i16_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: add a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB81_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw add ptr %a, i16 %b acquire
ret i16 %1
}
@@ -8206,47 +11804,99 @@ define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_add_i16_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NEXT: add a5, a3, a1
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB82_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: add a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB82_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_add_i16_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: add a5, a3, a1
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB82_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_add_i16_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: add a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB82_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i16_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: add a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB82_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_add_i16_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: add a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB82_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoadd.h.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw add ptr %a, i16 %b release
ret i16 %1
}
@@ -8314,47 +11964,99 @@ define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_add_i16_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: add a5, a3, a1
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB83_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: add a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB83_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_add_i16_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: add a5, a3, a1
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB83_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_add_i16_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: add a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB83_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i16_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: add a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB83_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_add_i16_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: add a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB83_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw add ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -8401,26 +12103,57 @@ define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_add_i16_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addi a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NEXT: add a5, a3, a1
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB84_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_add_i16_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NOZACAS-NEXT: add a5, a3, a1
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB84_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_add_i16_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a3, 16
+; RV64IA-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-ZACAS-NEXT: add a5, a3, a1
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB84_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw add ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -8467,26 +12200,59 @@ define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_sub_i16_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addi a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a3, (a2)
-; RV64IA-NEXT: sub a5, a3, a1
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB85_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i16_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-NOZACAS-NEXT: sub a5, a3, a1
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB85_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_sub_i16_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a3, 16
+; RV64IA-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-ZACAS-NEXT: sub a5, a3, a1
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB85_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
+; RV64IA-WMO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
+; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw sub ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -8554,47 +12320,101 @@ define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_sub_i16_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: sub a5, a3, a1
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB86_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: sub a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB86_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_sub_i16_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: sub a5, a3, a1
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB86_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i16_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: sub a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB86_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i16_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: sub a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB86_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_sub_i16_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: sub a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB86_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
+; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
+; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw sub ptr %a, i16 %b acquire
ret i16 %1
}
@@ -8662,47 +12482,101 @@ define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_sub_i16_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NEXT: sub a5, a3, a1
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB87_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: sub a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB87_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_sub_i16_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: sub a5, a3, a1
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB87_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i16_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: sub a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB87_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i16_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: sub a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB87_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_sub_i16_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: sub a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB87_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
+; RV64IA-WMO-ZABHA-NEXT: amoadd.h.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
+; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw sub ptr %a, i16 %b release
ret i16 %1
}
@@ -8770,47 +12644,101 @@ define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_sub_i16_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: sub a5, a3, a1
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB88_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: sub a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB88_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_sub_i16_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: sub a5, a3, a1
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB88_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i16_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: sub a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB88_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i16_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: sub a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB88_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_sub_i16_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: sub a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB88_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
+; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
+; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw sub ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -8857,26 +12785,59 @@ define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_sub_i16_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addi a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NEXT: sub a5, a3, a1
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB89_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_sub_i16_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NOZACAS-NEXT: sub a5, a3, a1
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB89_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_sub_i16_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a3, 16
+; RV64IA-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-ZACAS-NEXT: sub a5, a3, a1
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB89_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: neg a1, a1
+; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: neg a1, a1
+; RV64IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw sub ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -8917,20 +12878,45 @@ define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_and_i16_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addi a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: not a4, a4
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: or a1, a4, a1
-; RV64IA-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_and_i16_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-NOZACAS-NEXT: not a4, a4
+; RV64IA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-NOZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_and_i16_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a3, 16
+; RV64IA-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-ZACAS-NEXT: not a4, a4
+; RV64IA-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-ZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoand.h a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -8986,35 +12972,75 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_and_i16_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: not a4, a4
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: or a1, a4, a1
-; RV64IA-WMO-NEXT: amoand.w.aq a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a4, a4
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aq a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_and_i16_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: not a4, a4
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: or a1, a4, a1
-; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i16_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a4, a4
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: not a4, a4
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.aq a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i16_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: not a4, a4
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoand.h.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b acquire
ret i16 %1
}
@@ -9070,35 +13096,75 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_and_i16_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: not a4, a4
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: or a1, a4, a1
-; RV64IA-WMO-NEXT: amoand.w.rl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a4, a4
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.rl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_and_i16_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: not a4, a4
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: or a1, a4, a1
-; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i16_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a4, a4
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: not a4, a4
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.rl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i16_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: not a4, a4
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoand.h.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b release
ret i16 %1
}
@@ -9154,35 +13220,75 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_and_i16_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: not a4, a4
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: or a1, a4, a1
-; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a4, a4
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i16_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a4, a4
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: not a4, a4
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i16_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: not a4, a4
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoand.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_and_i16_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: not a4, a4
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: or a1, a4, a1
-; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -9238,35 +13344,75 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_and_i16_seq_cst:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: not a4, a4
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: or a1, a4, a1
-; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_seq_cst:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: not a4, a4
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_and_i16_seq_cst:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: not a4, a4
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: or a1, a4, a1
-; RV64IA-TSO-NEXT: amoand.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_and_i16_seq_cst:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: not a4, a4
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_seq_cst:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: not a4, a4
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_and_i16_seq_cst:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: not a4, a4
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: or a1, a4, a1
+; RV64IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoand.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw and ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -9314,27 +13460,123 @@ define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_nand_i16_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addi a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a3, (a2)
-; RV64IA-NEXT: and a5, a3, a1
-; RV64IA-NEXT: not a5, a5
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB95_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i16_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-NOZACAS-NEXT: not a5, a5
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB95_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_nand_i16_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a3, 16
+; RV64IA-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-ZACAS-NEXT: and a5, a3, a1
+; RV64IA-ZACAS-NEXT: not a5, a5
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB95_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_monotonic:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB95_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_monotonic:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB95_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_monotonic:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB95_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB95_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_monotonic:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB95_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB95_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -9404,49 +13646,167 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_nand_i16_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: and a5, a3, a1
-; RV64IA-WMO-NEXT: not a5, a5
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB96_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB96_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_nand_i16_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a5, a3, a1
-; RV64IA-TSO-NEXT: not a5, a5
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB96_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i16_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB96_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i16_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB96_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_nand_i16_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB96_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_acquire:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB96_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_acquire:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB96_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_acquire:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB96_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.h.aq a0, a3, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB96_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_acquire:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB96_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB96_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i16 %b acquire
ret i16 %1
}
@@ -9516,49 +13876,167 @@ define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_nand_i16_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NEXT: and a5, a3, a1
-; RV64IA-WMO-NEXT: not a5, a5
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB97_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB97_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_nand_i16_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a5, a3, a1
-; RV64IA-TSO-NEXT: not a5, a5
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB97_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i16_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB97_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i16_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB97_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_nand_i16_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB97_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_release:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB97_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_release:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB97_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_release:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB97_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.h.rl a0, a3, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB97_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_release:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB97_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB97_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i16 %b release
ret i16 %1
}
@@ -9628,49 +14106,167 @@ define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_nand_i16_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: and a5, a3, a1
-; RV64IA-WMO-NEXT: not a5, a5
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB98_1
-; RV64IA-WMO-NEXT: # %bb.2:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB98_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_nand_i16_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a5, a3, a1
-; RV64IA-TSO-NEXT: not a5, a5
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB98_1
-; RV64IA-TSO-NEXT: # %bb.2:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB98_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB98_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB98_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB98_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB98_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB98_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.h.aqrl a0, a3, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB98_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_acq_rel:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB98_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB98_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -9718,27 +14314,123 @@ define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_nand_i16_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addi a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NEXT: and a5, a3, a1
-; RV64IA-NEXT: not a5, a5
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB99_1
-; RV64IA-NEXT: # %bb.2:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_nand_i16_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-NOZACAS-NEXT: not a5, a5
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB99_1
+; RV64IA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_nand_i16_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a3, 16
+; RV64IA-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-ZACAS-NEXT: and a5, a3, a1
+; RV64IA-ZACAS-NEXT: not a5, a5
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB99_1
+; RV64IA-ZACAS-NEXT: # %bb.2:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_seq_cst:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB99_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_seq_cst:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB99_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_seq_cst:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB99_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.h.aqrl a0, a3, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB99_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_seq_cst:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB99_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 48
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 48
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB99_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -9775,16 +14467,37 @@ define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_or_i16_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: slli a1, a1, 48
-; RV64IA-NEXT: srli a1, a1, 48
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_or_i16_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_or_i16_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoor.h a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -9832,27 +14545,59 @@ define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_or_i16_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoor.w.aq a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aq a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_or_i16_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i16_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.aq a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i16_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoor.h.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b acquire
ret i16 %1
}
@@ -9900,27 +14645,59 @@ define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_or_i16_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoor.w.rl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.rl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_or_i16_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i16_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.rl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i16_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoor.h.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b release
ret i16 %1
}
@@ -9968,27 +14745,59 @@ define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_or_i16_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_or_i16_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i16_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i16_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoor.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -10036,27 +14845,59 @@ define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_or_i16_seq_cst:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_seq_cst:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_or_i16_seq_cst:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_or_i16_seq_cst:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_seq_cst:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_or_i16_seq_cst:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoor.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw or ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -10093,16 +14934,37 @@ define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xor_i16_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: slli a1, a1, 48
-; RV64IA-NEXT: srli a1, a1, 48
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_xor_i16_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_xor_i16_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoxor.h a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -10150,27 +15012,59 @@ define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xor_i16_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoxor.w.aq a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.aq a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xor_i16_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i16_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoxor.w.aq a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i16_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoxor.h.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b acquire
ret i16 %1
}
@@ -10218,27 +15112,59 @@ define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xor_i16_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoxor.w.rl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.rl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xor_i16_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i16_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoxor.w.rl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i16_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoxor.h.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b release
ret i16 %1
}
@@ -10286,27 +15212,59 @@ define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xor_i16_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xor_i16_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoxor.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -10354,27 +15312,59 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_xor_i16_seq_cst:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NEXT: srli a1, a1, 48
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2)
-; RV64IA-WMO-NEXT: srlw a0, a1, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_xor_i16_seq_cst:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NEXT: srli a1, a1, 48
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: amoxor.w a1, a1, (a2)
-; RV64IA-TSO-NEXT: srlw a0, a1, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2)
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: srli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2)
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amoxor.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw xor ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -10495,36 +15485,77 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_max_i16_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a3, a0, 24
-; RV64IA-NEXT: lui a4, 16
-; RV64IA-NEXT: addi a4, a4, -1
-; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: slli a1, a1, 48
-; RV64IA-NEXT: srai a1, a1, 48
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: li a5, 48
-; RV64IA-NEXT: sub a5, a5, a3
-; RV64IA-NEXT: .LBB110_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a3, (a2)
-; RV64IA-NEXT: and a7, a3, a4
-; RV64IA-NEXT: mv a6, a3
-; RV64IA-NEXT: sll a7, a7, a5
-; RV64IA-NEXT: sra a7, a7, a5
-; RV64IA-NEXT: bge a7, a1, .LBB110_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB110_1 Depth=1
-; RV64IA-NEXT: xor a6, a3, a1
-; RV64IA-NEXT: and a6, a6, a4
-; RV64IA-NEXT: xor a6, a3, a6
-; RV64IA-NEXT: .LBB110_3: # in Loop: Header=BB110_1 Depth=1
-; RV64IA-NEXT: sc.w a6, a6, (a2)
-; RV64IA-NEXT: bnez a6, .LBB110_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_max_i16_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-NOZACAS-NEXT: lui a4, 16
+; RV64IA-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: li a5, 48
+; RV64IA-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-NOZACAS-NEXT: .LBB110_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-NOZACAS-NEXT: mv a6, a3
+; RV64IA-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-NOZACAS-NEXT: bge a7, a1, .LBB110_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB110_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-NOZACAS-NEXT: .LBB110_3: # in Loop: Header=BB110_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a6, .LBB110_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_max_i16_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-ZACAS-NEXT: lui a4, 16
+; RV64IA-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: li a5, 48
+; RV64IA-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-ZACAS-NEXT: .LBB110_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-ZACAS-NEXT: mv a6, a3
+; RV64IA-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-ZACAS-NEXT: bge a7, a1, .LBB110_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB110_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-ZACAS-NEXT: .LBB110_3: # in Loop: Header=BB110_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-ZACAS-NEXT: bnez a6, .LBB110_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomax.h a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -10676,67 +15707,139 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_max_i16_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NEXT: lui a4, 16
-; RV64IA-WMO-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NEXT: srai a1, a1, 48
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: li a5, 48
-; RV64IA-WMO-NEXT: sub a5, a5, a3
-; RV64IA-WMO-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: and a7, a3, a4
-; RV64IA-WMO-NEXT: mv a6, a3
-; RV64IA-WMO-NEXT: sll a7, a7, a5
-; RV64IA-WMO-NEXT: sra a7, a7, a5
-; RV64IA-WMO-NEXT: bge a7, a1, .LBB111_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1
-; RV64IA-WMO-NEXT: xor a6, a3, a1
-; RV64IA-WMO-NEXT: and a6, a6, a4
-; RV64IA-WMO-NEXT: xor a6, a3, a6
-; RV64IA-WMO-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-WMO-NEXT: bnez a6, .LBB111_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NOZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: li a5, 48
+; RV64IA-WMO-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a6, a3
+; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB111_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-WMO-NOZACAS-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB111_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_max_i16_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NOZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: li a5, 48
+; RV64IA-TSO-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a6, a3
+; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB111_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-TSO-NOZACAS-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB111_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i16_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: li a5, 48
+; RV64IA-WMO-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a6, a3
+; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB111_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-WMO-ZACAS-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB111_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_max_i16_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: li a5, 48
+; RV64IA-TSO-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a6, a3
+; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB111_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-TSO-ZACAS-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB111_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_max_i16_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NEXT: lui a4, 16
-; RV64IA-TSO-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NEXT: srai a1, a1, 48
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: li a5, 48
-; RV64IA-TSO-NEXT: sub a5, a5, a3
-; RV64IA-TSO-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a7, a3, a4
-; RV64IA-TSO-NEXT: mv a6, a3
-; RV64IA-TSO-NEXT: sll a7, a7, a5
-; RV64IA-TSO-NEXT: sra a7, a7, a5
-; RV64IA-TSO-NEXT: bge a7, a1, .LBB111_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1
-; RV64IA-TSO-NEXT: xor a6, a3, a1
-; RV64IA-TSO-NEXT: and a6, a6, a4
-; RV64IA-TSO-NEXT: xor a6, a3, a6
-; RV64IA-TSO-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NEXT: bnez a6, .LBB111_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomax.h.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b acquire
ret i16 %1
}
@@ -10888,67 +15991,139 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_max_i16_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NEXT: lui a4, 16
-; RV64IA-WMO-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NEXT: srai a1, a1, 48
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: li a5, 48
-; RV64IA-WMO-NEXT: sub a5, a5, a3
-; RV64IA-WMO-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NEXT: and a7, a3, a4
-; RV64IA-WMO-NEXT: mv a6, a3
-; RV64IA-WMO-NEXT: sll a7, a7, a5
-; RV64IA-WMO-NEXT: sra a7, a7, a5
-; RV64IA-WMO-NEXT: bge a7, a1, .LBB112_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1
-; RV64IA-WMO-NEXT: xor a6, a3, a1
-; RV64IA-WMO-NEXT: and a6, a6, a4
-; RV64IA-WMO-NEXT: xor a6, a3, a6
-; RV64IA-WMO-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NEXT: bnez a6, .LBB112_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NOZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: li a5, 48
+; RV64IA-WMO-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a6, a3
+; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB112_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-WMO-NOZACAS-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB112_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_max_i16_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NEXT: lui a4, 16
-; RV64IA-TSO-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NEXT: srai a1, a1, 48
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: li a5, 48
-; RV64IA-TSO-NEXT: sub a5, a5, a3
-; RV64IA-TSO-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a7, a3, a4
-; RV64IA-TSO-NEXT: mv a6, a3
-; RV64IA-TSO-NEXT: sll a7, a7, a5
-; RV64IA-TSO-NEXT: sra a7, a7, a5
-; RV64IA-TSO-NEXT: bge a7, a1, .LBB112_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1
-; RV64IA-TSO-NEXT: xor a6, a3, a1
-; RV64IA-TSO-NEXT: and a6, a6, a4
-; RV64IA-TSO-NEXT: xor a6, a3, a6
-; RV64IA-TSO-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NEXT: bnez a6, .LBB112_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_max_i16_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NOZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: li a5, 48
+; RV64IA-TSO-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a6, a3
+; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB112_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-TSO-NOZACAS-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB112_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i16_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: li a5, 48
+; RV64IA-WMO-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a6, a3
+; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB112_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-WMO-ZACAS-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB112_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_max_i16_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: li a5, 48
+; RV64IA-TSO-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a6, a3
+; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB112_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-TSO-ZACAS-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB112_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomax.h.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b release
ret i16 %1
}
@@ -11100,67 +16275,139 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_max_i16_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NEXT: lui a4, 16
-; RV64IA-WMO-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NEXT: srai a1, a1, 48
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: li a5, 48
-; RV64IA-WMO-NEXT: sub a5, a5, a3
-; RV64IA-WMO-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: and a7, a3, a4
-; RV64IA-WMO-NEXT: mv a6, a3
-; RV64IA-WMO-NEXT: sll a7, a7, a5
-; RV64IA-WMO-NEXT: sra a7, a7, a5
-; RV64IA-WMO-NEXT: bge a7, a1, .LBB113_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1
-; RV64IA-WMO-NEXT: xor a6, a3, a1
-; RV64IA-WMO-NEXT: and a6, a6, a4
-; RV64IA-WMO-NEXT: xor a6, a3, a6
-; RV64IA-WMO-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NEXT: bnez a6, .LBB113_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NOZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: li a5, 48
+; RV64IA-WMO-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a6, a3
+; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB113_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-WMO-NOZACAS-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB113_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_max_i16_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NEXT: lui a4, 16
-; RV64IA-TSO-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NEXT: srai a1, a1, 48
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: li a5, 48
-; RV64IA-TSO-NEXT: sub a5, a5, a3
-; RV64IA-TSO-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a7, a3, a4
-; RV64IA-TSO-NEXT: mv a6, a3
-; RV64IA-TSO-NEXT: sll a7, a7, a5
-; RV64IA-TSO-NEXT: sra a7, a7, a5
-; RV64IA-TSO-NEXT: bge a7, a1, .LBB113_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1
-; RV64IA-TSO-NEXT: xor a6, a3, a1
-; RV64IA-TSO-NEXT: and a6, a6, a4
-; RV64IA-TSO-NEXT: xor a6, a3, a6
-; RV64IA-TSO-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NEXT: bnez a6, .LBB113_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_max_i16_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NOZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: li a5, 48
+; RV64IA-TSO-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a6, a3
+; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB113_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-TSO-NOZACAS-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB113_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i16_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: li a5, 48
+; RV64IA-WMO-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a6, a3
+; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB113_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-WMO-ZACAS-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB113_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_max_i16_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: li a5, 48
+; RV64IA-TSO-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a6, a3
+; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB113_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-TSO-ZACAS-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB113_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomax.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -11281,36 +16528,77 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_max_i16_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a3, a0, 24
-; RV64IA-NEXT: lui a4, 16
-; RV64IA-NEXT: addi a4, a4, -1
-; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: slli a1, a1, 48
-; RV64IA-NEXT: srai a1, a1, 48
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: li a5, 48
-; RV64IA-NEXT: sub a5, a5, a3
-; RV64IA-NEXT: .LBB114_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NEXT: and a7, a3, a4
-; RV64IA-NEXT: mv a6, a3
-; RV64IA-NEXT: sll a7, a7, a5
-; RV64IA-NEXT: sra a7, a7, a5
-; RV64IA-NEXT: bge a7, a1, .LBB114_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB114_1 Depth=1
-; RV64IA-NEXT: xor a6, a3, a1
-; RV64IA-NEXT: and a6, a6, a4
-; RV64IA-NEXT: xor a6, a3, a6
-; RV64IA-NEXT: .LBB114_3: # in Loop: Header=BB114_1 Depth=1
-; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-NEXT: bnez a6, .LBB114_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_max_i16_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-NOZACAS-NEXT: lui a4, 16
+; RV64IA-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: li a5, 48
+; RV64IA-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-NOZACAS-NEXT: .LBB114_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-NOZACAS-NEXT: mv a6, a3
+; RV64IA-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-NOZACAS-NEXT: bge a7, a1, .LBB114_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB114_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-NOZACAS-NEXT: .LBB114_3: # in Loop: Header=BB114_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a6, .LBB114_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_max_i16_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-ZACAS-NEXT: lui a4, 16
+; RV64IA-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: li a5, 48
+; RV64IA-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-ZACAS-NEXT: .LBB114_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-ZACAS-NEXT: mv a6, a3
+; RV64IA-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-ZACAS-NEXT: bge a7, a1, .LBB114_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB114_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-ZACAS-NEXT: .LBB114_3: # in Loop: Header=BB114_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-ZACAS-NEXT: bnez a6, .LBB114_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomax.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -11431,36 +16719,77 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_min_i16_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a3, a0, 24
-; RV64IA-NEXT: lui a4, 16
-; RV64IA-NEXT: addi a4, a4, -1
-; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: slli a1, a1, 48
-; RV64IA-NEXT: srai a1, a1, 48
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: li a5, 48
-; RV64IA-NEXT: sub a5, a5, a3
-; RV64IA-NEXT: .LBB115_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a3, (a2)
-; RV64IA-NEXT: and a7, a3, a4
-; RV64IA-NEXT: mv a6, a3
-; RV64IA-NEXT: sll a7, a7, a5
-; RV64IA-NEXT: sra a7, a7, a5
-; RV64IA-NEXT: bge a1, a7, .LBB115_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB115_1 Depth=1
-; RV64IA-NEXT: xor a6, a3, a1
-; RV64IA-NEXT: and a6, a6, a4
-; RV64IA-NEXT: xor a6, a3, a6
-; RV64IA-NEXT: .LBB115_3: # in Loop: Header=BB115_1 Depth=1
-; RV64IA-NEXT: sc.w a6, a6, (a2)
-; RV64IA-NEXT: bnez a6, .LBB115_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_min_i16_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-NOZACAS-NEXT: lui a4, 16
+; RV64IA-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: li a5, 48
+; RV64IA-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-NOZACAS-NEXT: .LBB115_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-NOZACAS-NEXT: mv a6, a3
+; RV64IA-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-NOZACAS-NEXT: bge a1, a7, .LBB115_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB115_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-NOZACAS-NEXT: .LBB115_3: # in Loop: Header=BB115_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a6, .LBB115_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_min_i16_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-ZACAS-NEXT: lui a4, 16
+; RV64IA-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: li a5, 48
+; RV64IA-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-ZACAS-NEXT: .LBB115_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-ZACAS-NEXT: mv a6, a3
+; RV64IA-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-ZACAS-NEXT: bge a1, a7, .LBB115_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB115_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-ZACAS-NEXT: .LBB115_3: # in Loop: Header=BB115_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-ZACAS-NEXT: bnez a6, .LBB115_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomin.h a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -11612,67 +16941,139 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_min_i16_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NEXT: lui a4, 16
-; RV64IA-WMO-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NEXT: srai a1, a1, 48
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: li a5, 48
-; RV64IA-WMO-NEXT: sub a5, a5, a3
-; RV64IA-WMO-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: and a7, a3, a4
-; RV64IA-WMO-NEXT: mv a6, a3
-; RV64IA-WMO-NEXT: sll a7, a7, a5
-; RV64IA-WMO-NEXT: sra a7, a7, a5
-; RV64IA-WMO-NEXT: bge a1, a7, .LBB116_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1
-; RV64IA-WMO-NEXT: xor a6, a3, a1
-; RV64IA-WMO-NEXT: and a6, a6, a4
-; RV64IA-WMO-NEXT: xor a6, a3, a6
-; RV64IA-WMO-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-WMO-NEXT: bnez a6, .LBB116_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NOZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: li a5, 48
+; RV64IA-WMO-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a6, a3
+; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB116_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-WMO-NOZACAS-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB116_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_min_i16_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NEXT: lui a4, 16
-; RV64IA-TSO-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NEXT: srai a1, a1, 48
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: li a5, 48
-; RV64IA-TSO-NEXT: sub a5, a5, a3
-; RV64IA-TSO-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a7, a3, a4
-; RV64IA-TSO-NEXT: mv a6, a3
-; RV64IA-TSO-NEXT: sll a7, a7, a5
-; RV64IA-TSO-NEXT: sra a7, a7, a5
-; RV64IA-TSO-NEXT: bge a1, a7, .LBB116_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1
-; RV64IA-TSO-NEXT: xor a6, a3, a1
-; RV64IA-TSO-NEXT: and a6, a6, a4
-; RV64IA-TSO-NEXT: xor a6, a3, a6
-; RV64IA-TSO-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NEXT: bnez a6, .LBB116_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_min_i16_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NOZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: li a5, 48
+; RV64IA-TSO-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a6, a3
+; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB116_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-TSO-NOZACAS-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB116_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i16_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: li a5, 48
+; RV64IA-WMO-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a6, a3
+; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB116_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-WMO-ZACAS-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB116_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_min_i16_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: li a5, 48
+; RV64IA-TSO-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a6, a3
+; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB116_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-TSO-ZACAS-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB116_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomin.h.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b acquire
ret i16 %1
}
@@ -11824,67 +17225,139 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_min_i16_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NEXT: lui a4, 16
-; RV64IA-WMO-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NEXT: srai a1, a1, 48
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: li a5, 48
-; RV64IA-WMO-NEXT: sub a5, a5, a3
-; RV64IA-WMO-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NEXT: and a7, a3, a4
-; RV64IA-WMO-NEXT: mv a6, a3
-; RV64IA-WMO-NEXT: sll a7, a7, a5
-; RV64IA-WMO-NEXT: sra a7, a7, a5
-; RV64IA-WMO-NEXT: bge a1, a7, .LBB117_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1
-; RV64IA-WMO-NEXT: xor a6, a3, a1
-; RV64IA-WMO-NEXT: and a6, a6, a4
-; RV64IA-WMO-NEXT: xor a6, a3, a6
-; RV64IA-WMO-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NEXT: bnez a6, .LBB117_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NOZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: li a5, 48
+; RV64IA-WMO-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a6, a3
+; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB117_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-WMO-NOZACAS-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB117_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_min_i16_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NEXT: lui a4, 16
-; RV64IA-TSO-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NEXT: srai a1, a1, 48
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: li a5, 48
-; RV64IA-TSO-NEXT: sub a5, a5, a3
-; RV64IA-TSO-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a7, a3, a4
-; RV64IA-TSO-NEXT: mv a6, a3
-; RV64IA-TSO-NEXT: sll a7, a7, a5
-; RV64IA-TSO-NEXT: sra a7, a7, a5
-; RV64IA-TSO-NEXT: bge a1, a7, .LBB117_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1
-; RV64IA-TSO-NEXT: xor a6, a3, a1
-; RV64IA-TSO-NEXT: and a6, a6, a4
-; RV64IA-TSO-NEXT: xor a6, a3, a6
-; RV64IA-TSO-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NEXT: bnez a6, .LBB117_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_min_i16_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NOZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: li a5, 48
+; RV64IA-TSO-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a6, a3
+; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB117_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-TSO-NOZACAS-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB117_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i16_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: li a5, 48
+; RV64IA-WMO-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a6, a3
+; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB117_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-WMO-ZACAS-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB117_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_min_i16_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: li a5, 48
+; RV64IA-TSO-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a6, a3
+; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB117_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-TSO-ZACAS-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB117_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomin.h.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b release
ret i16 %1
}
@@ -12036,67 +17509,139 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_min_i16_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: andi a3, a0, 24
-; RV64IA-WMO-NEXT: lui a4, 16
-; RV64IA-WMO-NEXT: addi a4, a4, -1
-; RV64IA-WMO-NEXT: sllw a4, a4, a0
-; RV64IA-WMO-NEXT: slli a1, a1, 48
-; RV64IA-WMO-NEXT: srai a1, a1, 48
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: li a5, 48
-; RV64IA-WMO-NEXT: sub a5, a5, a3
-; RV64IA-WMO-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: and a7, a3, a4
-; RV64IA-WMO-NEXT: mv a6, a3
-; RV64IA-WMO-NEXT: sll a7, a7, a5
-; RV64IA-WMO-NEXT: sra a7, a7, a5
-; RV64IA-WMO-NEXT: bge a1, a7, .LBB118_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1
-; RV64IA-WMO-NEXT: xor a6, a3, a1
-; RV64IA-WMO-NEXT: and a6, a6, a4
-; RV64IA-WMO-NEXT: xor a6, a3, a6
-; RV64IA-WMO-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-WMO-NEXT: bnez a6, .LBB118_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-NOZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: li a5, 48
+; RV64IA-WMO-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a6, a3
+; RV64IA-WMO-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-WMO-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB118_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-WMO-NOZACAS-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a6, .LBB118_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_min_i16_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: andi a3, a0, 24
-; RV64IA-TSO-NEXT: lui a4, 16
-; RV64IA-TSO-NEXT: addi a4, a4, -1
-; RV64IA-TSO-NEXT: sllw a4, a4, a0
-; RV64IA-TSO-NEXT: slli a1, a1, 48
-; RV64IA-TSO-NEXT: srai a1, a1, 48
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: li a5, 48
-; RV64IA-TSO-NEXT: sub a5, a5, a3
-; RV64IA-TSO-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a7, a3, a4
-; RV64IA-TSO-NEXT: mv a6, a3
-; RV64IA-TSO-NEXT: sll a7, a7, a5
-; RV64IA-TSO-NEXT: sra a7, a7, a5
-; RV64IA-TSO-NEXT: bge a1, a7, .LBB118_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1
-; RV64IA-TSO-NEXT: xor a6, a3, a1
-; RV64IA-TSO-NEXT: and a6, a6, a4
-; RV64IA-TSO-NEXT: xor a6, a3, a6
-; RV64IA-TSO-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a6, a6, (a2)
-; RV64IA-TSO-NEXT: bnez a6, .LBB118_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_min_i16_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-NOZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: li a5, 48
+; RV64IA-TSO-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a6, a3
+; RV64IA-TSO-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-TSO-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB118_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-TSO-NOZACAS-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a6, .LBB118_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i16_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-WMO-ZACAS-NEXT: lui a4, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-WMO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: li a5, 48
+; RV64IA-WMO-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-WMO-ZACAS-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a6, a3
+; RV64IA-WMO-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-WMO-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB118_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-WMO-ZACAS-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a6, .LBB118_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_min_i16_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-TSO-ZACAS-NEXT: lui a4, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-TSO-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: li a5, 48
+; RV64IA-TSO-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-TSO-ZACAS-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a6, a3
+; RV64IA-TSO-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-TSO-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB118_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-TSO-ZACAS-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a6, .LBB118_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomin.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -12217,36 +17762,77 @@ define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_min_i16_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: andi a3, a0, 24
-; RV64IA-NEXT: lui a4, 16
-; RV64IA-NEXT: addi a4, a4, -1
-; RV64IA-NEXT: sllw a4, a4, a0
-; RV64IA-NEXT: slli a1, a1, 48
-; RV64IA-NEXT: srai a1, a1, 48
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: li a5, 48
-; RV64IA-NEXT: sub a5, a5, a3
-; RV64IA-NEXT: .LBB119_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NEXT: and a7, a3, a4
-; RV64IA-NEXT: mv a6, a3
-; RV64IA-NEXT: sll a7, a7, a5
-; RV64IA-NEXT: sra a7, a7, a5
-; RV64IA-NEXT: bge a1, a7, .LBB119_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB119_1 Depth=1
-; RV64IA-NEXT: xor a6, a3, a1
-; RV64IA-NEXT: and a6, a6, a4
-; RV64IA-NEXT: xor a6, a3, a6
-; RV64IA-NEXT: .LBB119_3: # in Loop: Header=BB119_1 Depth=1
-; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
-; RV64IA-NEXT: bnez a6, .LBB119_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_min_i16_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: andi a3, a0, 24
+; RV64IA-NOZACAS-NEXT: lui a4, 16
+; RV64IA-NOZACAS-NEXT: addi a4, a4, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-NOZACAS-NEXT: slli a1, a1, 48
+; RV64IA-NOZACAS-NEXT: srai a1, a1, 48
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: li a5, 48
+; RV64IA-NOZACAS-NEXT: sub a5, a5, a3
+; RV64IA-NOZACAS-NEXT: .LBB119_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NOZACAS-NEXT: and a7, a3, a4
+; RV64IA-NOZACAS-NEXT: mv a6, a3
+; RV64IA-NOZACAS-NEXT: sll a7, a7, a5
+; RV64IA-NOZACAS-NEXT: sra a7, a7, a5
+; RV64IA-NOZACAS-NEXT: bge a1, a7, .LBB119_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB119_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a6, a3, a1
+; RV64IA-NOZACAS-NEXT: and a6, a6, a4
+; RV64IA-NOZACAS-NEXT: xor a6, a3, a6
+; RV64IA-NOZACAS-NEXT: .LBB119_3: # in Loop: Header=BB119_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a6, .LBB119_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_min_i16_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: andi a3, a0, 24
+; RV64IA-ZACAS-NEXT: lui a4, 16
+; RV64IA-ZACAS-NEXT: addi a4, a4, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a4, a0
+; RV64IA-ZACAS-NEXT: slli a1, a1, 48
+; RV64IA-ZACAS-NEXT: srai a1, a1, 48
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: li a5, 48
+; RV64IA-ZACAS-NEXT: sub a5, a5, a3
+; RV64IA-ZACAS-NEXT: .LBB119_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-ZACAS-NEXT: and a7, a3, a4
+; RV64IA-ZACAS-NEXT: mv a6, a3
+; RV64IA-ZACAS-NEXT: sll a7, a7, a5
+; RV64IA-ZACAS-NEXT: sra a7, a7, a5
+; RV64IA-ZACAS-NEXT: bge a1, a7, .LBB119_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB119_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a6, a3, a1
+; RV64IA-ZACAS-NEXT: and a6, a6, a4
+; RV64IA-ZACAS-NEXT: xor a6, a3, a6
+; RV64IA-ZACAS-NEXT: .LBB119_3: # in Loop: Header=BB119_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w.rl a6, a6, (a2)
+; RV64IA-ZACAS-NEXT: bnez a6, .LBB119_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomin.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -12365,30 +17951,65 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umax_i16_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addi a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB120_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a3, (a2)
-; RV64IA-NEXT: and a6, a3, a4
-; RV64IA-NEXT: mv a5, a3
-; RV64IA-NEXT: bgeu a6, a1, .LBB120_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB120_1 Depth=1
-; RV64IA-NEXT: xor a5, a3, a1
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: .LBB120_3: # in Loop: Header=BB120_1 Depth=1
-; RV64IA-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB120_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i16_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB120_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-NOZACAS-NEXT: mv a5, a3
+; RV64IA-NOZACAS-NEXT: bgeu a6, a1, .LBB120_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB120_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: .LBB120_3: # in Loop: Header=BB120_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB120_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_umax_i16_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a3, 16
+; RV64IA-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB120_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-ZACAS-NEXT: mv a5, a3
+; RV64IA-ZACAS-NEXT: bgeu a6, a1, .LBB120_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB120_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: .LBB120_3: # in Loop: Header=BB120_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB120_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomaxu.h a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -12532,55 +18153,115 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_umax_i16_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: and a6, a3, a4
-; RV64IA-WMO-NEXT: mv a5, a3
-; RV64IA-WMO-NEXT: bgeu a6, a1, .LBB121_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a3, a1
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB121_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB121_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB121_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_umax_i16_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a6, a3, a4
-; RV64IA-TSO-NEXT: mv a5, a3
-; RV64IA-TSO-NEXT: bgeu a6, a1, .LBB121_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a3, a1
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB121_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i16_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB121_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB121_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i16_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a3
+; RV64IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB121_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB121_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umax_i16_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a3
+; RV64IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB121_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB121_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomaxu.h.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b acquire
ret i16 %1
}
@@ -12724,55 +18405,115 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_umax_i16_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NEXT: and a6, a3, a4
-; RV64IA-WMO-NEXT: mv a5, a3
-; RV64IA-WMO-NEXT: bgeu a6, a1, .LBB122_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a3, a1
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB122_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB122_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB122_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_umax_i16_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a6, a3, a4
-; RV64IA-TSO-NEXT: mv a5, a3
-; RV64IA-TSO-NEXT: bgeu a6, a1, .LBB122_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a3, a1
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB122_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i16_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB122_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB122_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i16_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a3
+; RV64IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB122_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB122_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umax_i16_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a3
+; RV64IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB122_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB122_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomaxu.h.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b release
ret i16 %1
}
@@ -12916,55 +18657,115 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_umax_i16_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: and a6, a3, a4
-; RV64IA-WMO-NEXT: mv a5, a3
-; RV64IA-WMO-NEXT: bgeu a6, a1, .LBB123_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a3, a1
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB123_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB123_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB123_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_umax_i16_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a6, a3, a4
-; RV64IA-TSO-NEXT: mv a5, a3
-; RV64IA-TSO-NEXT: bgeu a6, a1, .LBB123_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a3, a1
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB123_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i16_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB123_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB123_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i16_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a3
+; RV64IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB123_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB123_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umax_i16_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a3
+; RV64IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB123_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB123_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomaxu.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -13083,30 +18884,65 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umax_i16_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addi a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB124_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NEXT: and a6, a3, a4
-; RV64IA-NEXT: mv a5, a3
-; RV64IA-NEXT: bgeu a6, a1, .LBB124_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB124_1 Depth=1
-; RV64IA-NEXT: xor a5, a3, a1
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: .LBB124_3: # in Loop: Header=BB124_1 Depth=1
-; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB124_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_umax_i16_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB124_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-NOZACAS-NEXT: mv a5, a3
+; RV64IA-NOZACAS-NEXT: bgeu a6, a1, .LBB124_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB124_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: .LBB124_3: # in Loop: Header=BB124_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB124_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_umax_i16_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a3, 16
+; RV64IA-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB124_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-ZACAS-NEXT: mv a5, a3
+; RV64IA-ZACAS-NEXT: bgeu a6, a1, .LBB124_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB124_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: .LBB124_3: # in Loop: Header=BB124_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB124_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amomaxu.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -13225,30 +19061,65 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umin_i16_monotonic:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addi a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB125_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w a3, (a2)
-; RV64IA-NEXT: and a6, a3, a4
-; RV64IA-NEXT: mv a5, a3
-; RV64IA-NEXT: bgeu a1, a6, .LBB125_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB125_1 Depth=1
-; RV64IA-NEXT: xor a5, a3, a1
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: .LBB125_3: # in Loop: Header=BB125_1 Depth=1
-; RV64IA-NEXT: sc.w a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB125_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i16_monotonic:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB125_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-NOZACAS-NEXT: mv a5, a3
+; RV64IA-NOZACAS-NEXT: bgeu a1, a6, .LBB125_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB125_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: .LBB125_3: # in Loop: Header=BB125_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB125_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_umin_i16_monotonic:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a3, 16
+; RV64IA-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB125_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-ZACAS-NEXT: mv a5, a3
+; RV64IA-ZACAS-NEXT: bgeu a1, a6, .LBB125_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB125_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: .LBB125_3: # in Loop: Header=BB125_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB125_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_monotonic:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amominu.h a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_monotonic:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b monotonic
ret i16 %1
}
@@ -13392,55 +19263,115 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_umin_i16_acquire:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: and a6, a3, a4
-; RV64IA-WMO-NEXT: mv a5, a3
-; RV64IA-WMO-NEXT: bgeu a1, a6, .LBB126_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a3, a1
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB126_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_acquire:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB126_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB126_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_umin_i16_acquire:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a6, a3, a4
-; RV64IA-TSO-NEXT: mv a5, a3
-; RV64IA-TSO-NEXT: bgeu a1, a6, .LBB126_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a3, a1
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB126_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i16_acquire:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB126_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB126_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i16_acquire:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a3
+; RV64IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB126_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB126_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umin_i16_acquire:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a3
+; RV64IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB126_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB126_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_acquire:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amominu.h.aq a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_acquire:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b acquire
ret i16 %1
}
@@ -13584,55 +19515,115 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_umin_i16_release:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w a3, (a2)
-; RV64IA-WMO-NEXT: and a6, a3, a4
-; RV64IA-WMO-NEXT: mv a5, a3
-; RV64IA-WMO-NEXT: bgeu a1, a6, .LBB127_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a3, a1
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB127_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_release:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB127_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB127_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_umin_i16_release:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a6, a3, a4
-; RV64IA-TSO-NEXT: mv a5, a3
-; RV64IA-TSO-NEXT: bgeu a1, a6, .LBB127_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a3, a1
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB127_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i16_release:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB127_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB127_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i16_release:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a3
+; RV64IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB127_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB127_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umin_i16_release:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a3
+; RV64IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB127_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB127_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_release:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amominu.h.rl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_release:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b release
ret i16 %1
}
@@ -13776,55 +19767,115 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-WMO-LABEL: atomicrmw_umin_i16_acq_rel:
-; RV64IA-WMO: # %bb.0:
-; RV64IA-WMO-NEXT: andi a2, a0, -4
-; RV64IA-WMO-NEXT: slli a0, a0, 3
-; RV64IA-WMO-NEXT: lui a3, 16
-; RV64IA-WMO-NEXT: addi a3, a3, -1
-; RV64IA-WMO-NEXT: sllw a4, a3, a0
-; RV64IA-WMO-NEXT: and a1, a1, a3
-; RV64IA-WMO-NEXT: sllw a1, a1, a0
-; RV64IA-WMO-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-WMO-NEXT: lr.w.aq a3, (a2)
-; RV64IA-WMO-NEXT: and a6, a3, a4
-; RV64IA-WMO-NEXT: mv a5, a3
-; RV64IA-WMO-NEXT: bgeu a1, a6, .LBB128_3
-; RV64IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1
-; RV64IA-WMO-NEXT: xor a5, a3, a1
-; RV64IA-WMO-NEXT: and a5, a5, a4
-; RV64IA-WMO-NEXT: xor a5, a3, a5
-; RV64IA-WMO-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1
-; RV64IA-WMO-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-WMO-NEXT: bnez a5, .LBB128_1
-; RV64IA-WMO-NEXT: # %bb.4:
-; RV64IA-WMO-NEXT: srlw a0, a3, a0
-; RV64IA-WMO-NEXT: ret
+; RV64IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_acq_rel:
+; RV64IA-WMO-NOZACAS: # %bb.0:
+; RV64IA-WMO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-NOZACAS-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-WMO-NOZACAS-NEXT: mv a5, a3
+; RV64IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB128_3
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-WMO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-NOZACAS-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1
+; RV64IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-NOZACAS-NEXT: bnez a5, .LBB128_1
+; RV64IA-WMO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-NOZACAS-NEXT: ret
;
-; RV64IA-TSO-LABEL: atomicrmw_umin_i16_acq_rel:
-; RV64IA-TSO: # %bb.0:
-; RV64IA-TSO-NEXT: andi a2, a0, -4
-; RV64IA-TSO-NEXT: slli a0, a0, 3
-; RV64IA-TSO-NEXT: lui a3, 16
-; RV64IA-TSO-NEXT: addi a3, a3, -1
-; RV64IA-TSO-NEXT: sllw a4, a3, a0
-; RV64IA-TSO-NEXT: and a1, a1, a3
-; RV64IA-TSO-NEXT: sllw a1, a1, a0
-; RV64IA-TSO-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-TSO-NEXT: lr.w a3, (a2)
-; RV64IA-TSO-NEXT: and a6, a3, a4
-; RV64IA-TSO-NEXT: mv a5, a3
-; RV64IA-TSO-NEXT: bgeu a1, a6, .LBB128_3
-; RV64IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1
-; RV64IA-TSO-NEXT: xor a5, a3, a1
-; RV64IA-TSO-NEXT: and a5, a5, a4
-; RV64IA-TSO-NEXT: xor a5, a3, a5
-; RV64IA-TSO-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1
-; RV64IA-TSO-NEXT: sc.w a5, a5, (a2)
-; RV64IA-TSO-NEXT: bnez a5, .LBB128_1
-; RV64IA-TSO-NEXT: # %bb.4:
-; RV64IA-TSO-NEXT: srlw a0, a3, a0
-; RV64IA-TSO-NEXT: ret
+; RV64IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i16_acq_rel:
+; RV64IA-TSO-NOZACAS: # %bb.0:
+; RV64IA-TSO-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NOZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-NOZACAS-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-TSO-NOZACAS-NEXT: mv a5, a3
+; RV64IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB128_3
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-TSO-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-NOZACAS-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1
+; RV64IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-NOZACAS-NEXT: bnez a5, .LBB128_1
+; RV64IA-TSO-NOZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i16_acq_rel:
+; RV64IA-WMO-ZACAS: # %bb.0:
+; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-WMO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-WMO-ZACAS-NEXT: lui a3, 16
+; RV64IA-WMO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-WMO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-WMO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-WMO-ZACAS-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2)
+; RV64IA-WMO-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-WMO-ZACAS-NEXT: mv a5, a3
+; RV64IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB128_3
+; RV64IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-WMO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-WMO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-WMO-ZACAS-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1
+; RV64IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-WMO-ZACAS-NEXT: bnez a5, .LBB128_1
+; RV64IA-WMO-ZACAS-NEXT: # %bb.4:
+; RV64IA-WMO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-WMO-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZACAS-LABEL: atomicrmw_umin_i16_acq_rel:
+; RV64IA-TSO-ZACAS: # %bb.0:
+; RV64IA-TSO-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-TSO-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-TSO-ZACAS-NEXT: lui a3, 16
+; RV64IA-TSO-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-TSO-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-TSO-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-TSO-ZACAS-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZACAS-NEXT: lr.w a3, (a2)
+; RV64IA-TSO-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-TSO-ZACAS-NEXT: mv a5, a3
+; RV64IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB128_3
+; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-TSO-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-TSO-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-TSO-ZACAS-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1
+; RV64IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2)
+; RV64IA-TSO-ZACAS-NEXT: bnez a5, .LBB128_1
+; RV64IA-TSO-ZACAS-NEXT: # %bb.4:
+; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_acq_rel:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amominu.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_acq_rel:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b acq_rel
ret i16 %1
}
@@ -13943,30 +19994,65 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_umin_i16_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a2, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: lui a3, 16
-; RV64IA-NEXT: addi a3, a3, -1
-; RV64IA-NEXT: sllw a4, a3, a0
-; RV64IA-NEXT: and a1, a1, a3
-; RV64IA-NEXT: sllw a1, a1, a0
-; RV64IA-NEXT: .LBB129_1: # =>This Inner Loop Header: Depth=1
-; RV64IA-NEXT: lr.w.aqrl a3, (a2)
-; RV64IA-NEXT: and a6, a3, a4
-; RV64IA-NEXT: mv a5, a3
-; RV64IA-NEXT: bgeu a1, a6, .LBB129_3
-; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB129_1 Depth=1
-; RV64IA-NEXT: xor a5, a3, a1
-; RV64IA-NEXT: and a5, a5, a4
-; RV64IA-NEXT: xor a5, a3, a5
-; RV64IA-NEXT: .LBB129_3: # in Loop: Header=BB129_1 Depth=1
-; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
-; RV64IA-NEXT: bnez a5, .LBB129_1
-; RV64IA-NEXT: # %bb.4:
-; RV64IA-NEXT: srlw a0, a3, a0
-; RV64IA-NEXT: ret
+; RV64IA-NOZACAS-LABEL: atomicrmw_umin_i16_seq_cst:
+; RV64IA-NOZACAS: # %bb.0:
+; RV64IA-NOZACAS-NEXT: andi a2, a0, -4
+; RV64IA-NOZACAS-NEXT: slli a0, a0, 3
+; RV64IA-NOZACAS-NEXT: lui a3, 16
+; RV64IA-NOZACAS-NEXT: addi a3, a3, -1
+; RV64IA-NOZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-NOZACAS-NEXT: and a1, a1, a3
+; RV64IA-NOZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-NOZACAS-NEXT: .LBB129_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-NOZACAS-NEXT: and a6, a3, a4
+; RV64IA-NOZACAS-NEXT: mv a5, a3
+; RV64IA-NOZACAS-NEXT: bgeu a1, a6, .LBB129_3
+; RV64IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB129_1 Depth=1
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a1
+; RV64IA-NOZACAS-NEXT: and a5, a5, a4
+; RV64IA-NOZACAS-NEXT: xor a5, a3, a5
+; RV64IA-NOZACAS-NEXT: .LBB129_3: # in Loop: Header=BB129_1 Depth=1
+; RV64IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-NOZACAS-NEXT: bnez a5, .LBB129_1
+; RV64IA-NOZACAS-NEXT: # %bb.4:
+; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-NOZACAS-NEXT: ret
+;
+; RV64IA-ZACAS-LABEL: atomicrmw_umin_i16_seq_cst:
+; RV64IA-ZACAS: # %bb.0:
+; RV64IA-ZACAS-NEXT: andi a2, a0, -4
+; RV64IA-ZACAS-NEXT: slli a0, a0, 3
+; RV64IA-ZACAS-NEXT: lui a3, 16
+; RV64IA-ZACAS-NEXT: addi a3, a3, -1
+; RV64IA-ZACAS-NEXT: sllw a4, a3, a0
+; RV64IA-ZACAS-NEXT: and a1, a1, a3
+; RV64IA-ZACAS-NEXT: sllw a1, a1, a0
+; RV64IA-ZACAS-NEXT: .LBB129_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-ZACAS-NEXT: lr.w.aqrl a3, (a2)
+; RV64IA-ZACAS-NEXT: and a6, a3, a4
+; RV64IA-ZACAS-NEXT: mv a5, a3
+; RV64IA-ZACAS-NEXT: bgeu a1, a6, .LBB129_3
+; RV64IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB129_1 Depth=1
+; RV64IA-ZACAS-NEXT: xor a5, a3, a1
+; RV64IA-ZACAS-NEXT: and a5, a5, a4
+; RV64IA-ZACAS-NEXT: xor a5, a3, a5
+; RV64IA-ZACAS-NEXT: .LBB129_3: # in Loop: Header=BB129_1 Depth=1
+; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2)
+; RV64IA-ZACAS-NEXT: bnez a5, .LBB129_1
+; RV64IA-ZACAS-NEXT: # %bb.4:
+; RV64IA-ZACAS-NEXT: srlw a0, a3, a0
+; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_seq_cst:
+; RV64IA-WMO-ZABHA: # %bb.0:
+; RV64IA-WMO-ZABHA-NEXT: amominu.h.aqrl a0, a1, (a0)
+; RV64IA-WMO-ZABHA-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_seq_cst:
+; RV64IA-TSO-ZABHA: # %bb.0:
+; RV64IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0)
+; RV64IA-TSO-ZABHA-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b seq_cst
ret i16 %1
}
@@ -14901,6 +20987,58 @@ define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64IA-ZACAS-NEXT: bne a0, a3, .LBB150_1
; RV64IA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_monotonic:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB150_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_monotonic:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB150_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_monotonic:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB150_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB150_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_monotonic:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB150_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB150_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i32 %b monotonic
ret i32 %1
}
@@ -15029,6 +21167,58 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB151_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_acquire:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a2, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB151_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_acquire:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB151_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_acquire:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB151_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.w.aq a0, a4, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB151_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_acquire:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB151_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB151_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i32 %b acquire
ret i32 %1
}
@@ -15157,6 +21347,58 @@ define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB152_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_release:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a3, a3, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB152_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_release:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB152_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_release:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB152_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.w.rl a0, a4, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB152_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_release:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB152_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB152_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i32 %b release
ret i32 %1
}
@@ -15285,6 +21527,58 @@ define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB153_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_acq_rel:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a2, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a3, a3, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB153_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_acq_rel:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB153_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_acq_rel:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB153_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.w.aqrl a0, a4, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB153_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_acq_rel:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB153_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB153_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i32 %b acq_rel
ret i32 %1
}
@@ -15389,6 +21683,58 @@ define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB154_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_seq_cst:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a2, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a3, a3, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB154_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_seq_cst:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a2, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.w.rl a3, a3, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB154_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_seq_cst:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB154_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.w.aqrl a0, a4, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB154_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_seq_cst:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB154_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB154_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i32 %b seq_cst
ret i32 %1
}
@@ -18678,6 +25024,58 @@ define i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64IA-ZACAS-NEXT: bne a0, a3, .LBB205_1
; RV64IA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_monotonic:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB205_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.d a2, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.d a3, a3, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB205_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_monotonic:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB205_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.d a2, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.d a3, a3, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB205_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_monotonic:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB205_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.d a0, a4, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB205_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_monotonic:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB205_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.d a0, a4, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB205_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i64 %b monotonic
ret i64 %1
}
@@ -18764,6 +25162,58 @@ define i64 @atomicrmw_nand_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB206_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_acquire:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB206_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.d.aq a2, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.d a3, a3, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB206_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_acquire:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB206_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.d a2, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.d a3, a3, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB206_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_acquire:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB206_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.d.aq a0, a4, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB206_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_acquire:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB206_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.d a0, a4, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB206_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i64 %b acquire
ret i64 %1
}
@@ -18850,6 +25300,58 @@ define i64 @atomicrmw_nand_i64_release(ptr %a, i64 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB207_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_release:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB207_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.d a2, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.d.rl a3, a3, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB207_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_release:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB207_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.d a2, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.d a3, a3, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB207_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_release:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB207_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.d.rl a0, a4, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB207_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_release:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB207_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.d a0, a4, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB207_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i64 %b release
ret i64 %1
}
@@ -18936,6 +25438,58 @@ define i64 @atomicrmw_nand_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB208_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_acq_rel:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB208_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.d.aq a2, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.d.rl a3, a3, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB208_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_acq_rel:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB208_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.d a2, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.d a3, a3, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB208_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_acq_rel:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB208_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.d.aqrl a0, a4, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB208_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_acq_rel:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB208_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.d a0, a4, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB208_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i64 %b acq_rel
ret i64 %1
}
@@ -19010,6 +25564,58 @@ define i64 @atomicrmw_nand_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64IA-TSO-ZACAS-NEXT: bne a0, a3, .LBB209_1
; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
; RV64IA-TSO-ZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_seq_cst:
+; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB209_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: lr.d.aqrl a2, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: sc.d.rl a3, a3, (a0)
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB209_1
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-WMO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i64_seq_cst:
+; RV64IA-TSO-ZABHA-NOZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: .LBB209_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: lr.d.aqrl a2, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: sc.d.rl a3, a3, (a0)
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB209_1
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2:
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2
+; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret
+;
+; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_seq_cst:
+; RV64IA-WMO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: .LBB209_1: # %atomicrmw.start
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: amocas.d.aqrl a0, a4, (a2)
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB209_1
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-WMO-ZABHA-ZACAS-NEXT: ret
+;
+; RV64IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i64_seq_cst:
+; RV64IA-TSO-ZABHA-ZACAS: # %bb.0:
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ld a0, 0(a0)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: .LBB209_1: # %atomicrmw.start
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: amocas.d a0, a4, (a2)
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB209_1
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end
+; RV64IA-TSO-ZABHA-ZACAS-NEXT: ret
%1 = atomicrmw nand ptr %a, i64 %b seq_cst
ret i64 %1
}
diff --git a/llvm/test/Transforms/InstCombine/fsh.ll b/llvm/test/Transforms/InstCombine/fsh.ll
index 48bf296993f6ac..6c85169453d15a 100644
--- a/llvm/test/Transforms/InstCombine/fsh.ll
+++ b/llvm/test/Transforms/InstCombine/fsh.ll
@@ -722,6 +722,134 @@ define i32 @fsh_orconst_rotate(i32 %a) {
ret i32 %t2
}
+define i32 @fsh_rotate_5(i8 %x, i32 %y) {
+; CHECK-LABEL: @fsh_rotate_5(
+; CHECK-NEXT: [[T1:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[OR1:%.*]] = or i32 [[T1]], [[Y:%.*]]
+; CHECK-NEXT: [[OR2:%.*]] = call i32 @llvm.fshl.i32(i32 [[OR1]], i32 [[OR1]], i32 5)
+; CHECK-NEXT: ret i32 [[OR2]]
+;
+
+ %t1 = zext i8 %x to i32
+ %or1 = or i32 %t1, %y
+ %shr = lshr i32 %or1, 27
+ %shl = shl i32 %or1, 5
+ %or2 = or i32 %shr, %shl
+ ret i32 %or2
+}
+
+define i32 @fsh_rotate_18(i8 %x, i32 %y) {
+; CHECK-LABEL: @fsh_rotate_18(
+; CHECK-NEXT: [[T1:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[OR1:%.*]] = or i32 [[T1]], [[Y:%.*]]
+; CHECK-NEXT: [[OR2:%.*]] = call i32 @llvm.fshl.i32(i32 [[OR1]], i32 [[OR1]], i32 18)
+; CHECK-NEXT: ret i32 [[OR2]]
+;
+
+ %t1 = zext i8 %x to i32
+ %or1 = or i32 %t1, %y
+ %shr = lshr i32 %or1, 14
+ %shl = shl i32 %or1, 18
+ %or2 = or i32 %shr, %shl
+ ret i32 %or2
+}
+
+define i32 @fsh_load_rotate_12(ptr %data) {
+; CHECK-LABEL: @fsh_load_rotate_12(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[DATA:%.*]], align 1
+; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
+; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[CONV]], 24
+; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 1
+; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1
+; CHECK-NEXT: [[CONV2:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT: [[SHL3:%.*]] = shl nuw nsw i32 [[CONV2]], 16
+; CHECK-NEXT: [[OR:%.*]] = or disjoint i32 [[SHL3]], [[SHL]]
+; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 2
+; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
+; CHECK-NEXT: [[CONV5:%.*]] = zext i8 [[TMP2]] to i32
+; CHECK-NEXT: [[SHL6:%.*]] = shl nuw nsw i32 [[CONV5]], 8
+; CHECK-NEXT: [[OR7:%.*]] = or disjoint i32 [[OR]], [[SHL6]]
+; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 3
+; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1
+; CHECK-NEXT: [[CONV9:%.*]] = zext i8 [[TMP3]] to i32
+; CHECK-NEXT: [[OR10:%.*]] = or disjoint i32 [[OR7]], [[CONV9]]
+; CHECK-NEXT: [[OR15:%.*]] = call i32 @llvm.fshl.i32(i32 [[OR10]], i32 [[OR10]], i32 12)
+; CHECK-NEXT: ret i32 [[OR15]]
+;
+
+entry:
+ %0 = load i8, ptr %data
+ %conv = zext i8 %0 to i32
+ %shl = shl nuw i32 %conv, 24
+ %arrayidx1 = getelementptr inbounds i8, ptr %data, i64 1
+ %1 = load i8, ptr %arrayidx1
+ %conv2 = zext i8 %1 to i32
+ %shl3 = shl nuw nsw i32 %conv2, 16
+ %or = or i32 %shl3, %shl
+ %arrayidx4 = getelementptr inbounds i8, ptr %data, i64 2
+ %2 = load i8, ptr %arrayidx4
+ %conv5 = zext i8 %2 to i32
+ %shl6 = shl nuw nsw i32 %conv5, 8
+ %or7 = or i32 %or, %shl6
+ %arrayidx8 = getelementptr inbounds i8, ptr %data, i64 3
+ %3 = load i8, ptr %arrayidx8
+ %conv9 = zext i8 %3 to i32
+ %or10 = or i32 %or7, %conv9
+ %shr = lshr i32 %or10, 20
+ %shl7 = shl i32 %or10, 12
+ %or15 = or i32 %shr, %shl7
+ ret i32 %or15
+}
+
+define i32 @fsh_load_rotate_25(ptr %data) {
+; CHECK-LABEL: @fsh_load_rotate_25(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[DATA:%.*]], align 1
+; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
+; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[CONV]], 24
+; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 1
+; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1
+; CHECK-NEXT: [[CONV2:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT: [[SHL3:%.*]] = shl nuw nsw i32 [[CONV2]], 16
+; CHECK-NEXT: [[OR:%.*]] = or disjoint i32 [[SHL3]], [[SHL]]
+; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 2
+; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
+; CHECK-NEXT: [[CONV5:%.*]] = zext i8 [[TMP2]] to i32
+; CHECK-NEXT: [[SHL6:%.*]] = shl nuw nsw i32 [[CONV5]], 8
+; CHECK-NEXT: [[OR7:%.*]] = or disjoint i32 [[OR]], [[SHL6]]
+; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 3
+; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1
+; CHECK-NEXT: [[CONV9:%.*]] = zext i8 [[TMP3]] to i32
+; CHECK-NEXT: [[OR10:%.*]] = or disjoint i32 [[OR7]], [[CONV9]]
+; CHECK-NEXT: [[OR15:%.*]] = call i32 @llvm.fshl.i32(i32 [[OR10]], i32 [[OR10]], i32 25)
+; CHECK-NEXT: ret i32 [[OR15]]
+;
+
+entry:
+ %0 = load i8, ptr %data
+ %conv = zext i8 %0 to i32
+ %shl = shl nuw i32 %conv, 24
+ %arrayidx1 = getelementptr inbounds i8, ptr %data, i64 1
+ %1 = load i8, ptr %arrayidx1
+ %conv2 = zext i8 %1 to i32
+ %shl3 = shl nuw nsw i32 %conv2, 16
+ %or = or i32 %shl3, %shl
+ %arrayidx4 = getelementptr inbounds i8, ptr %data, i64 2
+ %2 = load i8, ptr %arrayidx4
+ %conv5 = zext i8 %2 to i32
+ %shl6 = shl nuw nsw i32 %conv5, 8
+ %or7 = or i32 %or, %shl6
+ %arrayidx8 = getelementptr inbounds i8, ptr %data, i64 3
+ %3 = load i8, ptr %arrayidx8
+ %conv9 = zext i8 %3 to i32
+ %or10 = or i32 %or7, %conv9
+ %shr = lshr i32 %or10, 7
+ %shl7 = shl i32 %or10, 25
+ %or15 = or i32 %shr, %shl7
+ ret i32 %or15
+}
+
define <2 x i31> @fshr_mask_args_same_vector(<2 x i31> %a) {
; CHECK-LABEL: @fshr_mask_args_same_vector(
; CHECK-NEXT: [[T3:%.*]] = shl <2 x i31> [[A:%.*]], <i31 10, i31 10>
diff --git a/llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll b/llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll
index 1042c413fbb7bb..996d2c0e67e165 100644
--- a/llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll
+++ b/llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll
@@ -38,8 +38,8 @@ define ptr @test2() {
define void @test3_multiple_fields(ptr nocapture %a, ptr nocapture %b) {
; CHECK-LABEL: @test3_multiple_fields(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[B:%.*]], align 4
-; CHECK-NEXT: store i64 [[TMP0]], ptr [[A:%.*]], align 4
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[B:%.*]], align 4, !tbaa.struct [[TBAA_STRUCT3:![0-9]+]]
+; CHECK-NEXT: store i64 [[TMP0]], ptr [[A:%.*]], align 4, !tbaa.struct [[TBAA_STRUCT3]]
; CHECK-NEXT: ret void
;
entry:
@@ -86,4 +86,5 @@ entry:
; CHECK: [[TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}
; CHECK: [[META1]] = !{!"float", [[META2:![0-9]+]]}
; CHECK: [[META2]] = !{!"Simple C/C++ TBAA"}
+; CHECK: [[TBAA_STRUCT3]] = !{i64 0, i64 4, [[TBAA0]], i64 4, i64 4, [[TBAA0]]}
;.
diff --git a/llvm/test/Transforms/LoopVectorize/trunc-reductions.ll b/llvm/test/Transforms/LoopVectorize/trunc-reductions.ll
index 2278821c5b2f9c..debb26b6329b71 100644
--- a/llvm/test/Transforms/LoopVectorize/trunc-reductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/trunc-reductions.ll
@@ -245,3 +245,68 @@ for.end:
%ret = trunc i32 %min to i16
ret i16 %ret
}
+
+; Test case for https://github.com/llvm/llvm-project/issues/81415.
+define i32 @reduction_and_or(i16 %a, i32 %b, ptr %src) {
+; CHECK-LABEL: @reduction_and_or(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK: vector.ph:
+; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
+; CHECK: vector.body:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <8 x i32> [ <i32 10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, [[VECTOR_PH]] ], [ [[TMP2:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[INDEX]] to i64
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC:%.*]], i64 [[TMP0]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, ptr [[TMP1]], align 4
+; CHECK-NEXT: [[TMP2]] = or <8 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 992
+; CHECK-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK: middle.block:
+; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> [[TMP2]])
+; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]]
+; CHECK: scalar.ph:
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[TMP4]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 992, [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[OR67:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[OR:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = zext nneg i32 [[IV]] to i64
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP5]]
+; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP]], align 4
+; CHECK-NEXT: [[OR]] = or i32 [[OR67]], [[L]]
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
+; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], 999
+; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK: exit:
+; CHECK-NEXT: [[OR_LCSSA:%.*]] = phi i32 [ [[OR]], [[LOOP]] ], [ poison, [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: ret i32 [[OR_LCSSA]]
+;
+entry:
+ %ext1 = zext i16 %a to i32
+ br label %loop
+
+loop:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
+ %or67 = phi i32 [ 10, %entry ], [ %or, %loop ]
+ %t = trunc i32 %b to i16
+ %ext = sext i16 %t to i32
+ %cmp = icmp sgt i32 %ext, %ext1
+ %ext2 = zext i1 %cmp to i32
+ %cmp3 = icmp sge i32 %iv, %ext2
+ %ext4 = zext i1 %cmp3 to i32
+ %div = sdiv i32 %ext4, %b
+ %and = and i32 %div, 0
+ %gep = getelementptr inbounds i32, ptr %src, i32 %iv
+ %l = load i32, ptr %gep
+ %add = add i32 %and, %l
+ %or = or i32 %or67, %add
+ %iv.next = add nsw i32 %iv, 1
+ %tobool.not = icmp eq i32 %iv.next, 999
+ br i1 %tobool.not, label %exit, label %loop
+
+exit:
+ %or.lcssa = phi i32 [ %or, %loop ]
+ ret i32 %or.lcssa
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/horizontal.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/horizontal.ll
index e0aa038005944c..1986b51ec94828 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/horizontal.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/horizontal.ll
@@ -32,14 +32,14 @@ define i32 @test_select(ptr noalias nocapture readonly %blk1, ptr noalias nocapt
; CHECK-NEXT: [[J_025:%.*]] = phi i32 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[P2_024:%.*]] = phi ptr [ [[BLK2:%.*]], [[FOR_BODY_LR_PH]] ], [ [[ADD_PTR29:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[P1_023:%.*]] = phi ptr [ [[BLK1:%.*]], [[FOR_BODY_LR_PH]] ], [ [[ADD_PTR:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P1_023]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[P2_024]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = sub nsw <4 x i32> [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = icmp slt <4 x i32> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = sub nsw <4 x i32> zeroinitializer, [[TMP4]]
-; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[TMP6]], <4 x i32> [[TMP4]]
-; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP7]])
-; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP8]], [[S_026]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[P1_023]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P2_024]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = sub nsw <4 x i32> [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <4 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: [[TMP4:%.*]] = sub nsw <4 x i32> zeroinitializer, [[TMP2]]
+; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> [[TMP2]]
+; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP5]])
+; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP6]], [[S_026]]
; CHECK-NEXT: [[ADD_PTR]] = getelementptr inbounds i32, ptr [[P1_023]], i64 [[IDX_EXT]]
; CHECK-NEXT: [[ADD_PTR29]] = getelementptr inbounds i32, ptr [[P2_024]], i64 [[IDX_EXT]]
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[J_025]], 1
@@ -150,11 +150,11 @@ define i32 @reduction_with_br(ptr noalias nocapture readonly %blk1, ptr noalias
; CHECK-NEXT: [[J_019:%.*]] = phi i32 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[IF_END]] ]
; CHECK-NEXT: [[P2_018:%.*]] = phi ptr [ [[BLK2:%.*]], [[FOR_BODY_LR_PH]] ], [ [[ADD_PTR16:%.*]], [[IF_END]] ]
; CHECK-NEXT: [[P1_017:%.*]] = phi ptr [ [[BLK1:%.*]], [[FOR_BODY_LR_PH]] ], [ [[ADD_PTR:%.*]], [[IF_END]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P1_017]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[P2_018]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = mul nsw <4 x i32> [[TMP3]], [[TMP1]]
-; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP4]])
-; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP5]], [[S_020]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[P1_017]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P2_018]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = mul nsw <4 x i32> [[TMP1]], [[TMP0]]
+; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])
+; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP3]], [[S_020]]
; CHECK-NEXT: [[CMP14:%.*]] = icmp slt i32 [[OP_RDX]], [[LIM:%.*]]
; CHECK-NEXT: br i1 [[CMP14]], label [[IF_END]], label [[FOR_END_LOOPEXIT:%.*]]
; CHECK: if.end:
@@ -245,16 +245,16 @@ define i32 @test_unrolled_select(ptr noalias nocapture readonly %blk1, ptr noali
; CHECK-NEXT: [[J_046:%.*]] = phi i32 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[IF_END_86]] ]
; CHECK-NEXT: [[P2_045:%.*]] = phi ptr [ [[BLK2:%.*]], [[FOR_BODY_LR_PH]] ], [ [[ADD_PTR88:%.*]], [[IF_END_86]] ]
; CHECK-NEXT: [[P1_044:%.*]] = phi ptr [ [[BLK1:%.*]], [[FOR_BODY_LR_PH]] ], [ [[ADD_PTR:%.*]], [[IF_END_86]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[P1_044]], align 1
-; CHECK-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[TMP1]] to <8 x i32>
-; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i8>, ptr [[P2_045]], align 1
-; CHECK-NEXT: [[TMP5:%.*]] = zext <8 x i8> [[TMP4]] to <8 x i32>
-; CHECK-NEXT: [[TMP6:%.*]] = sub nsw <8 x i32> [[TMP2]], [[TMP5]]
-; CHECK-NEXT: [[TMP7:%.*]] = icmp slt <8 x i32> [[TMP6]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = sub nsw <8 x i32> zeroinitializer, [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[TMP7]], <8 x i32> [[TMP8]], <8 x i32> [[TMP6]]
-; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP9]])
-; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP10]], [[S_047]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr [[P1_044]], align 1
+; CHECK-NEXT: [[TMP1:%.*]] = zext <8 x i8> [[TMP0]] to <8 x i32>
+; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[P2_045]], align 1
+; CHECK-NEXT: [[TMP3:%.*]] = zext <8 x i8> [[TMP2]] to <8 x i32>
+; CHECK-NEXT: [[TMP4:%.*]] = sub nsw <8 x i32> [[TMP1]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp slt <8 x i32> [[TMP4]], zeroinitializer
+; CHECK-NEXT: [[TMP6:%.*]] = sub nsw <8 x i32> zeroinitializer, [[TMP4]]
+; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP5]], <8 x i32> [[TMP6]], <8 x i32> [[TMP4]]
+; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP7]])
+; CHECK-NEXT: [[OP_RDX]] = add i32 [[TMP8]], [[S_047]]
; CHECK-NEXT: [[CMP83:%.*]] = icmp slt i32 [[OP_RDX]], [[LIM:%.*]]
; CHECK-NEXT: br i1 [[CMP83]], label [[IF_END_86]], label [[FOR_END_LOOPEXIT:%.*]]
; CHECK: if.end.86:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll b/llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
index 4132fbaa5c755f..4565d4928ba4ad 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
@@ -9,17 +9,17 @@ define { i64, i64 } @patatino(double %arg) {
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr @global, align 16
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr getelementptr inbounds ([6 x double], ptr @global, i64 0, i64 2), align 16
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[ARG:%.*]], i32 0
-; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> [[TMP1]], [[SHUFFLE]]
-; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP0]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([6 x double], ptr @global, i64 0, i64 4), align 16
-; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x double> [[TMP5]], [[TMP4]]
-; CHECK-NEXT: [[TMP7:%.*]] = fptosi <2 x double> [[TMP6]] to <2 x i32>
-; CHECK-NEXT: [[TMP8:%.*]] = sext <2 x i32> [[TMP7]] to <2 x i64>
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP8]], i32 0
-; CHECK-NEXT: [[T16:%.*]] = insertvalue { i64, i64 } undef, i64 [[TMP9]], 0
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP8]], i32 1
-; CHECK-NEXT: [[T17:%.*]] = insertvalue { i64, i64 } [[T16]], i64 [[TMP10]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP1]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[TMP0]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = load <2 x double>, ptr getelementptr inbounds ([6 x double], ptr @global, i64 0, i64 4), align 16
+; CHECK-NEXT: [[TMP7:%.*]] = fadd <2 x double> [[TMP6]], [[TMP5]]
+; CHECK-NEXT: [[TMP8:%.*]] = fptosi <2 x double> [[TMP7]] to <2 x i32>
+; CHECK-NEXT: [[TMP9:%.*]] = sext <2 x i32> [[TMP8]] to <2 x i64>
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP9]], i32 0
+; CHECK-NEXT: [[T16:%.*]] = insertvalue { i64, i64 } undef, i64 [[TMP10]], 0
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i64> [[TMP9]], i32 1
+; CHECK-NEXT: [[T17:%.*]] = insertvalue { i64, i64 } [[T16]], i64 [[TMP11]], 1
; CHECK-NEXT: ret { i64, i64 } [[T17]]
;
bb:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll b/llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll
index 903adc8893f346..651631de2c35ad 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll
@@ -20,13 +20,13 @@ define i8 @PR31243_zext(i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %ptr) {
; SSE-NEXT: [[TMP0:%.*]] = or i8 [[V0:%.*]], 1
; SSE-NEXT: [[TMP1:%.*]] = or i8 [[V1:%.*]], 1
; SSE-NEXT: [[TMP2:%.*]] = zext i8 [[TMP0]] to i64
-; SSE-NEXT: [[TMP_4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP2]]
+; SSE-NEXT: [[T4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP2]]
; SSE-NEXT: [[TMP3:%.*]] = zext i8 [[TMP1]] to i64
-; SSE-NEXT: [[TMP_5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP3]]
-; SSE-NEXT: [[TMP_6:%.*]] = load i8, ptr [[TMP_4]], align 1
-; SSE-NEXT: [[TMP_7:%.*]] = load i8, ptr [[TMP_5]], align 1
-; SSE-NEXT: [[TMP_8:%.*]] = add i8 [[TMP_6]], [[TMP_7]]
-; SSE-NEXT: ret i8 [[TMP_8]]
+; SSE-NEXT: [[T5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP3]]
+; SSE-NEXT: [[T6:%.*]] = load i8, ptr [[T4]], align 1
+; SSE-NEXT: [[T7:%.*]] = load i8, ptr [[T5]], align 1
+; SSE-NEXT: [[T8:%.*]] = add i8 [[T6]], [[T7]]
+; SSE-NEXT: ret i8 [[T8]]
;
; AVX-LABEL: @PR31243_zext(
; AVX-NEXT: entry:
@@ -35,26 +35,26 @@ define i8 @PR31243_zext(i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %ptr) {
; AVX-NEXT: [[TMP2:%.*]] = or <2 x i8> [[TMP1]], <i8 1, i8 1>
; AVX-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i64 0
; AVX-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64
-; AVX-NEXT: [[TMP_4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP4]]
+; AVX-NEXT: [[T4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP4]]
; AVX-NEXT: [[TMP5:%.*]] = extractelement <2 x i8> [[TMP2]], i64 1
; AVX-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i64
-; AVX-NEXT: [[TMP_5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP6]]
-; AVX-NEXT: [[TMP_6:%.*]] = load i8, ptr [[TMP_4]], align 1
-; AVX-NEXT: [[TMP_7:%.*]] = load i8, ptr [[TMP_5]], align 1
-; AVX-NEXT: [[TMP_8:%.*]] = add i8 [[TMP_6]], [[TMP_7]]
-; AVX-NEXT: ret i8 [[TMP_8]]
+; AVX-NEXT: [[T5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP6]]
+; AVX-NEXT: [[T6:%.*]] = load i8, ptr [[T4]], align 1
+; AVX-NEXT: [[T7:%.*]] = load i8, ptr [[T5]], align 1
+; AVX-NEXT: [[T8:%.*]] = add i8 [[T6]], [[T7]]
+; AVX-NEXT: ret i8 [[T8]]
;
entry:
- %tmp_0 = zext i8 %v0 to i32
- %tmp_1 = zext i8 %v1 to i32
- %tmp_2 = or i32 %tmp_0, 1
- %tmp_3 = or i32 %tmp_1, 1
- %tmp_4 = getelementptr inbounds i8, ptr %ptr, i32 %tmp_2
- %tmp_5 = getelementptr inbounds i8, ptr %ptr, i32 %tmp_3
- %tmp_6 = load i8, ptr %tmp_4
- %tmp_7 = load i8, ptr %tmp_5
- %tmp_8 = add i8 %tmp_6, %tmp_7
- ret i8 %tmp_8
+ %t0 = zext i8 %v0 to i32
+ %t1 = zext i8 %v1 to i32
+ %t2 = or i32 %t0, 1
+ %t3 = or i32 %t1, 1
+ %t4 = getelementptr inbounds i8, ptr %ptr, i32 %t2
+ %t5 = getelementptr inbounds i8, ptr %ptr, i32 %t3
+ %t6 = load i8, ptr %t4
+ %t7 = load i8, ptr %t5
+ %t8 = add i8 %t6, %t7
+ ret i8 %t8
}
; When computing minimum sizes, if we cannot prove the sign bit is zero, we
@@ -76,13 +76,13 @@ define i8 @PR31243_sext(i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %ptr) {
; SSE-NEXT: [[TMP0:%.*]] = or i8 [[V0:%.*]], 1
; SSE-NEXT: [[TMP1:%.*]] = or i8 [[V1:%.*]], 1
; SSE-NEXT: [[TMP2:%.*]] = sext i8 [[TMP0]] to i64
-; SSE-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP2]]
+; SSE-NEXT: [[T4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP2]]
; SSE-NEXT: [[TMP3:%.*]] = sext i8 [[TMP1]] to i64
-; SSE-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP3]]
-; SSE-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP4]], align 1
-; SSE-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP5]], align 1
-; SSE-NEXT: [[TMP8:%.*]] = add i8 [[TMP6]], [[TMP7]]
-; SSE-NEXT: ret i8 [[TMP8]]
+; SSE-NEXT: [[T5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP3]]
+; SSE-NEXT: [[T6:%.*]] = load i8, ptr [[T4]], align 1
+; SSE-NEXT: [[T7:%.*]] = load i8, ptr [[T5]], align 1
+; SSE-NEXT: [[T8:%.*]] = add i8 [[T6]], [[T7]]
+; SSE-NEXT: ret i8 [[T8]]
;
; AVX-LABEL: @PR31243_sext(
; AVX-NEXT: entry:
@@ -92,24 +92,24 @@ define i8 @PR31243_sext(i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %ptr) {
; AVX-NEXT: [[TMP3:%.*]] = sext <2 x i8> [[TMP2]] to <2 x i16>
; AVX-NEXT: [[TMP4:%.*]] = extractelement <2 x i16> [[TMP3]], i64 0
; AVX-NEXT: [[TMP5:%.*]] = sext i16 [[TMP4]] to i64
-; AVX-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP5]]
+; AVX-NEXT: [[T4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i64 [[TMP5]]
; AVX-NEXT: [[TMP6:%.*]] = extractelement <2 x i16> [[TMP3]], i64 1
; AVX-NEXT: [[TMP7:%.*]] = sext i16 [[TMP6]] to i64
-; AVX-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP7]]
-; AVX-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP4]], align 1
-; AVX-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP5]], align 1
-; AVX-NEXT: [[TMP8:%.*]] = add i8 [[TMP6]], [[TMP7]]
-; AVX-NEXT: ret i8 [[TMP8]]
+; AVX-NEXT: [[T5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[TMP7]]
+; AVX-NEXT: [[T6:%.*]] = load i8, ptr [[T4]], align 1
+; AVX-NEXT: [[T7:%.*]] = load i8, ptr [[T5]], align 1
+; AVX-NEXT: [[T8:%.*]] = add i8 [[T6]], [[T7]]
+; AVX-NEXT: ret i8 [[T8]]
;
entry:
- %tmp0 = sext i8 %v0 to i32
- %tmp1 = sext i8 %v1 to i32
- %tmp2 = or i32 %tmp0, 1
- %tmp3 = or i32 %tmp1, 1
- %tmp4 = getelementptr inbounds i8, ptr %ptr, i32 %tmp2
- %tmp5 = getelementptr inbounds i8, ptr %ptr, i32 %tmp3
- %tmp6 = load i8, ptr %tmp4
- %tmp7 = load i8, ptr %tmp5
- %tmp8 = add i8 %tmp6, %tmp7
- ret i8 %tmp8
+ %t0 = sext i8 %v0 to i32
+ %t1 = sext i8 %v1 to i32
+ %t2 = or i32 %t0, 1
+ %t3 = or i32 %t1, 1
+ %t4 = getelementptr inbounds i8, ptr %ptr, i32 %t2
+ %t5 = getelementptr inbounds i8, ptr %ptr, i32 %t3
+ %t6 = load i8, ptr %t4
+ %t7 = load i8, ptr %t5
+ %t8 = add i8 %t6, %t7
+ ret i8 %t8
}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/multi-node-with-save-values.ll b/llvm/test/Transforms/SLPVectorizer/X86/multi-node-with-save-values.ll
index 2088a3db212bed..1a129f6ed80505 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/multi-node-with-save-values.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/multi-node-with-save-values.ll
@@ -7,9 +7,9 @@ define void @foo() {
; CHECK-NEXT: br label [[BB1:%.*]]
; CHECK: bb1:
; CHECK-NEXT: switch i32 0, label [[BB3:%.*]] [
-; CHECK-NEXT: i32 0, label [[BB2:%.*]]
-; CHECK-NEXT: i32 4, label [[BB4:%.*]]
-; CHECK-NEXT: i32 1, label [[BB4]]
+; CHECK-NEXT: i32 0, label [[BB2:%.*]]
+; CHECK-NEXT: i32 4, label [[BB4:%.*]]
+; CHECK-NEXT: i32 1, label [[BB4]]
; CHECK-NEXT: ]
; CHECK: bb2:
; CHECK-NEXT: br label [[BB4]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vectorize-cmps.ll b/llvm/test/Transforms/SLPVectorizer/X86/vectorize-cmps.ll
index b2e0af3b58ce53..b8a2d8431b1e6b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vectorize-cmps.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vectorize-cmps.ll
@@ -4,13 +4,13 @@
define i32 @test(ptr %isec, float %0) {
; CHECK-LABEL: @test(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[ISEC:%.*]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[TMP0:%.*]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = fmul fast <2 x float> [[TMP3]], [[TMP2]]
+; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[ISEC:%.*]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[TMP0:%.*]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <2 x float> [[TMP2]], [[TMP1]]
; CHECK-NEXT: [[CMP61:%.*]] = fcmp fast oge float 0.000000e+00, 0.000000e+00
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP4]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x float> [[TMP4]], i32 1
-; CHECK-NEXT: [[CMP63:%.*]] = fcmp fast ogt float [[TMP5]], [[TMP6]]
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP3]], i32 1
+; CHECK-NEXT: [[CMP63:%.*]] = fcmp fast ogt float [[TMP4]], [[TMP5]]
; CHECK-NEXT: br i1 [[CMP63]], label [[CLEANUP:%.*]], label [[IF_END:%.*]]
; CHECK: if.end:
; CHECK-NEXT: br label [[CLEANUP]]
diff --git a/llvm/test/Transforms/SROA/tbaa-struct2.ll b/llvm/test/Transforms/SROA/tbaa-struct2.ll
index 1fd37e82d67775..02c99a2b329457 100644
--- a/llvm/test/Transforms/SROA/tbaa-struct2.ll
+++ b/llvm/test/Transforms/SROA/tbaa-struct2.ll
@@ -13,9 +13,9 @@ define double @bar(ptr %wishart) {
; CHECK-NEXT: [[TMP_SROA_3:%.*]] = alloca [4 x i8], align 4
; CHECK-NEXT: [[TMP_SROA_0_0_COPYLOAD:%.*]] = load double, ptr [[WISHART:%.*]], align 8, !tbaa.struct [[TBAA_STRUCT0:![0-9]+]]
; CHECK-NEXT: [[TMP_SROA_2_0_WISHART_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[WISHART]], i64 8
-; CHECK-NEXT: [[TMP_SROA_2_0_COPYLOAD:%.*]] = load i32, ptr [[TMP_SROA_2_0_WISHART_SROA_IDX]], align 8, !tbaa.struct [[TBAA_STRUCT7:![0-9]+]]
+; CHECK-NEXT: [[TMP_SROA_2_0_COPYLOAD:%.*]] = load i32, ptr [[TMP_SROA_2_0_WISHART_SROA_IDX]], align 8, !tbaa [[TBAA5:![0-9]+]]
; CHECK-NEXT: [[TMP_SROA_3_0_WISHART_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[WISHART]], i64 12
-; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP_SROA_3]], ptr align 4 [[TMP_SROA_3_0_WISHART_SROA_IDX]], i64 4, i1 false), !tbaa.struct [[TBAA_STRUCT8:![0-9]+]]
+; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP_SROA_3]], ptr align 4 [[TMP_SROA_3_0_WISHART_SROA_IDX]], i64 4, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]]
; CHECK-NEXT: [[CALL:%.*]] = call double @subcall(double [[TMP_SROA_0_0_COPYLOAD]], i32 [[TMP_SROA_2_0_COPYLOAD]])
; CHECK-NEXT: ret double [[CALL]]
;
@@ -38,15 +38,14 @@ define double @bar(ptr %wishart) {
;.
; CHECK: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
;.
-; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 8, !1, i64 8, i64 4, !5}
-; CHECK: [[META1:![0-9]+]] = !{!2, !2, i64 0}
-; CHECK: [[META2:![0-9]+]] = !{!"double", !3, i64 0}
-; CHECK: [[META3:![0-9]+]] = !{!"omnipotent char", !4, i64 0}
-; CHECK: [[META4:![0-9]+]] = !{!"Simple C++ TBAA"}
-; CHECK: [[META5:![0-9]+]] = !{!6, !6, i64 0}
-; CHECK: [[META6:![0-9]+]] = !{!"int", !3, i64 0}
-; CHECK: [[TBAA_STRUCT7]] = !{i64 0, i64 4, !5}
-; CHECK: [[TBAA_STRUCT8]] = !{}
+; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 8, [[META1:![0-9]+]], i64 8, i64 4, [[TBAA5]]}
+; CHECK: [[META1]] = !{[[META2:![0-9]+]], [[META2]], i64 0}
+; CHECK: [[META2]] = !{!"double", [[META3:![0-9]+]], i64 0}
+; CHECK: [[META3]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0}
+; CHECK: [[META4]] = !{!"Simple C++ TBAA"}
+; CHECK: [[TBAA5]] = !{[[META6:![0-9]+]], [[META6]], i64 0}
+; CHECK: [[META6]] = !{!"int", [[META3]], i64 0}
+; CHECK: [[TBAA_STRUCT7]] = !{}
;.
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-MODIFY-CFG: {{.*}}
diff --git a/llvm/test/Transforms/SROA/tbaa-struct3.ll b/llvm/test/Transforms/SROA/tbaa-struct3.ll
index 71a4a126710aa2..2a151c01adfcc0 100644
--- a/llvm/test/Transforms/SROA/tbaa-struct3.ll
+++ b/llvm/test/Transforms/SROA/tbaa-struct3.ll
@@ -10,9 +10,9 @@ define void @load_store_transfer_split_struct_tbaa_2_float(ptr dereferenceable(2
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[A]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[B]] to i32
-; CHECK-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4
+; CHECK-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4, !tbaa.struct [[TBAA_STRUCT0:![0-9]+]]
; CHECK-NEXT: [[RES_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[RES]], i64 4
-; CHECK-NEXT: store i32 [[TMP1]], ptr [[RES_SROA_IDX]], align 4
+; CHECK-NEXT: store i32 [[TMP1]], ptr [[RES_SROA_IDX]], align 4, !tbaa [[TBAA1:![0-9]+]]
; CHECK-NEXT: [[P:%.*]] = load ptr, ptr [[RES]], align 8
; CHECK-NEXT: ret void
;
@@ -32,9 +32,9 @@ define void @memcpy_transfer(ptr dereferenceable(24) %res, float %a, float %b) {
; CHECK-SAME: ptr dereferenceable(24) [[RES:%.*]], float [[A:%.*]], float [[B:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[L_PTR:%.*]] = load ptr, ptr [[RES]], align 8
-; CHECK-NEXT: store float [[A]], ptr [[L_PTR]], align 1, !tbaa.struct [[TBAA_STRUCT0:![0-9]+]]
+; CHECK-NEXT: store float [[A]], ptr [[L_PTR]], align 1, !tbaa.struct [[TBAA_STRUCT0]]
; CHECK-NEXT: [[TMP_SROA_2_0_L_PTR_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[L_PTR]], i64 4
-; CHECK-NEXT: store float [[B]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa.struct [[TBAA_STRUCT5:![0-9]+]]
+; CHECK-NEXT: store float [[B]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa [[TBAA1]]
; CHECK-NEXT: ret void
;
entry:
@@ -56,7 +56,7 @@ define void @memcpy_transfer_tbaa_field_and_size_do_not_align(ptr dereferenceabl
; CHECK-NEXT: [[TMP_SROA_2_0_L_PTR_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[L_PTR]], i64 4
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[B]] to i32
; CHECK-NEXT: [[TMP_SROA_2_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[TMP0]] to i16
-; CHECK-NEXT: store i16 [[TMP_SROA_2_0_EXTRACT_TRUNC]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa.struct [[TBAA_STRUCT5]]
+; CHECK-NEXT: store i16 [[TMP_SROA_2_0_EXTRACT_TRUNC]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa.struct [[TBAA_STRUCT5:![0-9]+]]
; CHECK-NEXT: ret void
;
entry:
@@ -100,7 +100,7 @@ define void @store_vector_part_first(ptr %y2, float %f) {
; CHECK-NEXT: [[V_1:%.*]] = call <2 x float> @foo(ptr [[Y2]])
; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[Y2]], align 8, !tbaa.struct [[TBAA_STRUCT6:![0-9]+]]
; CHECK-NEXT: [[X7_SROA_2_0_Y2_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[Y2]], i64 8
-; CHECK-NEXT: store float [[F]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 8, !tbaa.struct [[TBAA_STRUCT5]]
+; CHECK-NEXT: store float [[F]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 8, !tbaa [[TBAA1]]
; CHECK-NEXT: ret void
;
%x7 = alloca { float, float, float, float }
@@ -118,7 +118,7 @@ define void @store_vector_part_second(ptr %y2, float %f) {
; CHECK-NEXT: [[V_1:%.*]] = call <2 x float> @foo(ptr [[Y2]])
; CHECK-NEXT: store float [[F]], ptr [[Y2]], align 8, !tbaa.struct [[TBAA_STRUCT9:![0-9]+]]
; CHECK-NEXT: [[X7_SROA_2_0_Y2_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[Y2]], i64 4
-; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 4, !tbaa.struct [[TBAA_STRUCT10:![0-9]+]]
+; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 4, !tbaa [[TBAA7:![0-9]+]]
; CHECK-NEXT: ret void
;
%x7 = alloca { float, float, float, float }
@@ -134,7 +134,7 @@ define void @store_vector_single(ptr %y2, float %f) {
; CHECK-LABEL: define void @store_vector_single(
; CHECK-SAME: ptr [[Y2:%.*]], float [[F:%.*]]) {
; CHECK-NEXT: [[V_1:%.*]] = call <2 x float> @foo(ptr [[Y2]])
-; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[Y2]], align 4, !tbaa.struct [[TBAA_STRUCT11:![0-9]+]]
+; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[Y2]], align 4, !tbaa.struct [[TBAA_STRUCT10:![0-9]+]]
; CHECK-NEXT: ret void
;
%x7 = alloca { float, float }
@@ -161,8 +161,8 @@ define void @memset(ptr %dst, ptr align 8 %src) {
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[A_SROA_4]], ptr align 1 [[A_SROA_4_0_SRC_SROA_IDX]], i32 10, i1 false)
; CHECK-NEXT: store i16 1, ptr [[A_SROA_3]], align 2
; CHECK-NEXT: [[A_SROA_0_1_A_1_SROA_IDX2:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_0]], i64 1
-; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_1_A_1_SROA_IDX2]], i8 42, i32 6, i1 false), !tbaa.struct [[TBAA_STRUCT12:![0-9]+]]
-; CHECK-NEXT: store i16 10794, ptr [[A_SROA_3]], align 2, !tbaa.struct [[TBAA_STRUCT13:![0-9]+]]
+; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_1_A_1_SROA_IDX2]], i8 42, i32 6, i1 false), !tbaa.struct [[TBAA_STRUCT11:![0-9]+]]
+; CHECK-NEXT: store i16 10794, ptr [[A_SROA_3]], align 2, !tbaa [[TBAA1]]
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 1 [[A_SROA_0]], i32 7, i1 true)
; CHECK-NEXT: [[A_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 7
; CHECK-NEXT: [[A_SROA_3_0_A_SROA_3_0_COPYLOAD1:%.*]] = load volatile i16, ptr [[A_SROA_3]], align 2
@@ -199,8 +199,8 @@ define void @memset2(ptr %dst, ptr align 8 %src) {
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[A_SROA_4]], ptr align 2 [[A_SROA_4_0_SRC_SROA_IDX]], i32 90, i1 false)
; CHECK-NEXT: store i8 1, ptr [[A_SROA_3]], align 1
; CHECK-NEXT: [[A_SROA_0_202_A_202_SROA_IDX2:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_0]], i64 202
-; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_202_A_202_SROA_IDX2]], i8 42, i32 7, i1 false), !tbaa.struct [[TBAA_STRUCT14:![0-9]+]]
-; CHECK-NEXT: store i8 42, ptr [[A_SROA_3]], align 1, !tbaa.struct [[TBAA_STRUCT15:![0-9]+]]
+; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_202_A_202_SROA_IDX2]], i8 42, i32 7, i1 false), !tbaa.struct [[TBAA_STRUCT12:![0-9]+]]
+; CHECK-NEXT: store i8 42, ptr [[A_SROA_3]], align 1, !tbaa [[TBAA7]]
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 1 [[A_SROA_0]], i32 209, i1 true)
; CHECK-NEXT: [[A_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 209
; CHECK-NEXT: [[A_SROA_3_0_A_SROA_3_0_COPYLOAD1:%.*]] = load volatile i8, ptr [[A_SROA_3]], align 1
@@ -240,7 +240,7 @@ define void @slice_store_v2i8_1(ptr %dst, ptr %dst.2, ptr %src) {
; CHECK-NEXT: [[A_SROA_2_0_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 6
; CHECK-NEXT: [[A_SROA_2_SROA_0_0_COPYLOAD:%.*]] = load <2 x i8>, ptr [[A_SROA_2_0_SRC_SROA_IDX]], align 2
; CHECK-NEXT: store <2 x i8> [[A_SROA_2_SROA_0_0_COPYLOAD]], ptr [[A_SROA_2_SROA_0]], align 4
-; CHECK-NEXT: store <2 x i8> bitcast (<1 x i16> <i16 123> to <2 x i8>), ptr [[A_SROA_2_SROA_0]], align 4, !tbaa.struct [[TBAA_STRUCT16:![0-9]+]]
+; CHECK-NEXT: store <2 x i8> bitcast (<1 x i16> <i16 123> to <2 x i8>), ptr [[A_SROA_2_SROA_0]], align 4, !tbaa.struct [[TBAA_STRUCT13:![0-9]+]]
; CHECK-NEXT: [[A_SROA_2_SROA_0_0_A_SROA_2_SROA_0_0_A_SROA_2_6_V_4:%.*]] = load <2 x i8>, ptr [[A_SROA_2_SROA_0]], align 4
; CHECK-NEXT: store <2 x i8> [[A_SROA_2_SROA_0_0_A_SROA_2_SROA_0_0_A_SROA_2_6_V_4]], ptr [[DST_2]], align 2
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 1 [[A_SROA_0]], i32 6, i1 true)
@@ -279,8 +279,8 @@ define void @slice_store_v2i8_2(ptr %dst, ptr %dst.2, ptr %src) {
; CHECK-NEXT: store i8 [[A_SROA_0_SROA_4_1_COPYLOAD]], ptr [[A_SROA_0_SROA_4]], align 1
; CHECK-NEXT: [[A_SROA_4_1_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 3
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[A_SROA_4]], ptr align 1 [[A_SROA_4_1_SRC_SROA_IDX]], i32 5, i1 false)
-; CHECK-NEXT: store <2 x i8> zeroinitializer, ptr [[A_SROA_0_SROA_1]], align 2, !tbaa.struct [[TBAA_STRUCT17:![0-9]+]]
-; CHECK-NEXT: store i8 0, ptr [[A_SROA_0_SROA_4]], align 1, !tbaa.struct [[TBAA_STRUCT18:![0-9]+]]
+; CHECK-NEXT: store <2 x i8> zeroinitializer, ptr [[A_SROA_0_SROA_1]], align 2, !tbaa.struct [[TBAA_STRUCT14:![0-9]+]]
+; CHECK-NEXT: store i8 0, ptr [[A_SROA_0_SROA_4]], align 1, !tbaa [[TBAA1]]
; CHECK-NEXT: [[A_SROA_0_SROA_1_0_A_SROA_0_SROA_1_1_A_SROA_0_1_V_4:%.*]] = load <2 x i8>, ptr [[A_SROA_0_SROA_1]], align 2
; CHECK-NEXT: store <2 x i8> [[A_SROA_0_SROA_1_0_A_SROA_0_SROA_1_1_A_SROA_0_1_V_4]], ptr [[DST_2]], align 2
; CHECK-NEXT: [[A_SROA_0_SROA_1_0_A_SROA_0_SROA_1_1_COPYLOAD3:%.*]] = load volatile <2 x i8>, ptr [[A_SROA_0_SROA_1]], align 2
@@ -317,7 +317,7 @@ define double @tbaa_struct_load(ptr %src, ptr %dst) {
; CHECK-NEXT: [[TMP_SROA_3_0_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 8
; CHECK-NEXT: [[TMP_SROA_3_0_COPYLOAD:%.*]] = load i64, ptr [[TMP_SROA_3_0_SRC_SROA_IDX]], align 8
; CHECK-NEXT: store i64 [[TMP_SROA_3_0_COPYLOAD]], ptr [[TMP_SROA_3]], align 8
-; CHECK-NEXT: [[TMP_SROA_0_0_TMP_SROA_0_0_LG:%.*]] = load double, ptr [[TMP_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT10]]
+; CHECK-NEXT: [[TMP_SROA_0_0_TMP_SROA_0_0_LG:%.*]] = load double, ptr [[TMP_SROA_0]], align 8, !tbaa [[TBAA7]]
; CHECK-NEXT: [[TMP_SROA_0_0_TMP_SROA_0_0_COPYLOAD1:%.*]] = load volatile double, ptr [[TMP_SROA_0]], align 8
; CHECK-NEXT: store volatile double [[TMP_SROA_0_0_TMP_SROA_0_0_COPYLOAD1]], ptr [[DST]], align 8
; CHECK-NEXT: [[TMP_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 8
@@ -356,7 +356,7 @@ define i32 @shorten_integer_store_multiple_fields(ptr %dst, ptr %dst.2, ptr %src
; CHECK-SAME: ptr [[DST:%.*]], ptr [[DST_2:%.*]], ptr [[SRC:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca i32, align 4
-; CHECK-NEXT: store i32 123, ptr [[A_SROA_0]], align 4, !tbaa.struct [[TBAA_STRUCT19:![0-9]+]]
+; CHECK-NEXT: store i32 123, ptr [[A_SROA_0]], align 4, !tbaa [[TBAA7]]
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_L:%.*]] = load i32, ptr [[A_SROA_0]], align 4
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_COPYLOAD:%.*]] = load volatile i32, ptr [[A_SROA_0]], align 4
; CHECK-NEXT: store volatile i32 [[A_SROA_0_0_A_SROA_0_0_COPYLOAD]], ptr [[DST]], align 1
@@ -393,7 +393,7 @@ define <2 x i16> @shorten_vector_store_single_fields(ptr %dst, ptr %dst.2, ptr %
; CHECK-SAME: ptr [[DST:%.*]], ptr [[DST_2:%.*]], ptr [[SRC:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca <2 x i32>, align 8
-; CHECK-NEXT: store <2 x i32> <i32 1, i32 2>, ptr [[A_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT19]]
+; CHECK-NEXT: store <2 x i32> <i32 1, i32 2>, ptr [[A_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT15:![0-9]+]]
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_L:%.*]] = load <2 x i16>, ptr [[A_SROA_0]], align 8
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 8 [[A_SROA_0]], i32 4, i1 true)
; CHECK-NEXT: ret <2 x i16> [[A_SROA_0_0_A_SROA_0_0_L]]
@@ -429,11 +429,11 @@ define i32 @split_load_with_tbaa_struct(i32 %x, ptr %src, ptr %dst) {
; CHECK-NEXT: [[A3_SROA_5_0_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 9
; CHECK-NEXT: [[A3_SROA_5_0_COPYLOAD:%.*]] = load i8, ptr [[A3_SROA_5_0_SRC_SROA_IDX]], align 1
; CHECK-NEXT: store i8 [[A3_SROA_5_0_COPYLOAD]], ptr [[A3_SROA_5]], align 1
-; CHECK-NEXT: [[A3_SROA_0_0_A3_SROA_0_0_LOAD4_FCA_0_LOAD:%.*]] = load i16, ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT20:![0-9]+]]
+; CHECK-NEXT: [[A3_SROA_0_0_A3_SROA_0_0_LOAD4_FCA_0_LOAD:%.*]] = load i16, ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT16:![0-9]+]]
; CHECK-NEXT: [[LOAD4_FCA_0_INSERT:%.*]] = insertvalue { i16, float, i8 } poison, i16 [[A3_SROA_0_0_A3_SROA_0_0_LOAD4_FCA_0_LOAD]], 0
-; CHECK-NEXT: [[A3_SROA_33_0_A3_SROA_33_4_LOAD4_FCA_1_LOAD:%.*]] = load float, ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT21:![0-9]+]]
+; CHECK-NEXT: [[A3_SROA_33_0_A3_SROA_33_4_LOAD4_FCA_1_LOAD:%.*]] = load float, ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT17:![0-9]+]]
; CHECK-NEXT: [[LOAD4_FCA_1_INSERT:%.*]] = insertvalue { i16, float, i8 } [[LOAD4_FCA_0_INSERT]], float [[A3_SROA_33_0_A3_SROA_33_4_LOAD4_FCA_1_LOAD]], 1
-; CHECK-NEXT: [[A3_SROA_4_0_A3_SROA_4_8_LOAD4_FCA_2_LOAD:%.*]] = load i8, ptr [[A3_SROA_4]], align 8, !tbaa.struct [[TBAA_STRUCT15]]
+; CHECK-NEXT: [[A3_SROA_4_0_A3_SROA_4_8_LOAD4_FCA_2_LOAD:%.*]] = load i8, ptr [[A3_SROA_4]], align 8, !tbaa [[TBAA7]]
; CHECK-NEXT: [[LOAD4_FCA_2_INSERT:%.*]] = insertvalue { i16, float, i8 } [[LOAD4_FCA_1_INSERT]], i8 [[A3_SROA_4_0_A3_SROA_4_8_LOAD4_FCA_2_LOAD]], 2
; CHECK-NEXT: [[UNWRAP2:%.*]] = extractvalue { i16, float, i8 } [[LOAD4_FCA_2_INSERT]], 1
; CHECK-NEXT: [[VALCAST2:%.*]] = bitcast float [[UNWRAP2]] to i32
@@ -492,11 +492,11 @@ define i32 @split_store_with_tbaa_struct(i32 %x, ptr %src, ptr %dst) {
; CHECK-NEXT: [[I_2:%.*]] = insertvalue { i16, float, i8 } [[I_1]], float 3.000000e+00, 1
; CHECK-NEXT: [[I_3:%.*]] = insertvalue { i16, float, i8 } [[I_2]], i8 99, 2
; CHECK-NEXT: [[I_3_FCA_0_EXTRACT:%.*]] = extractvalue { i16, float, i8 } [[I_3]], 0
-; CHECK-NEXT: store i16 [[I_3_FCA_0_EXTRACT]], ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT20]]
+; CHECK-NEXT: store i16 [[I_3_FCA_0_EXTRACT]], ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT16]]
; CHECK-NEXT: [[I_3_FCA_1_EXTRACT:%.*]] = extractvalue { i16, float, i8 } [[I_3]], 1
-; CHECK-NEXT: store float [[I_3_FCA_1_EXTRACT]], ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT21]]
+; CHECK-NEXT: store float [[I_3_FCA_1_EXTRACT]], ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT17]]
; CHECK-NEXT: [[I_3_FCA_2_EXTRACT:%.*]] = extractvalue { i16, float, i8 } [[I_3]], 2
-; CHECK-NEXT: store i8 [[I_3_FCA_2_EXTRACT]], ptr [[A3_SROA_4]], align 8, !tbaa.struct [[TBAA_STRUCT15]]
+; CHECK-NEXT: store i8 [[I_3_FCA_2_EXTRACT]], ptr [[A3_SROA_4]], align 8, !tbaa [[TBAA7]]
; CHECK-NEXT: [[A3_SROA_0_0_A3_SROA_0_0_COPYLOAD1:%.*]] = load volatile i16, ptr [[A3_SROA_0]], align 8
; CHECK-NEXT: store volatile i16 [[A3_SROA_0_0_A3_SROA_0_0_COPYLOAD1]], ptr [[DST]], align 1
; CHECK-NEXT: [[A3_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 2
@@ -548,26 +548,22 @@ declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias
!15 = !{i64 0, i64 7, !6, i64 7, i64 1, !6}
!16 = !{i64 0, i64 2, !6, i64 4, i64 4, !6, i64 8, i64 1, !6}
;.
-; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 4, [[META1:![0-9]+]], i64 4, i64 4, [[META1]]}
-; CHECK: [[META1]] = !{[[META2:![0-9]+]], [[META2]], i64 0}
+; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 4, [[TBAA1]], i64 4, i64 4, [[TBAA1]]}
+; CHECK: [[TBAA1]] = !{[[META2:![0-9]+]], [[META2]], i64 0}
; CHECK: [[META2]] = !{!"float", [[META3:![0-9]+]], i64 0}
; CHECK: [[META3]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0}
; CHECK: [[META4]] = !{!"Simple C++ TBAA"}
-; CHECK: [[TBAA_STRUCT5]] = !{i64 0, i64 4, [[META1]]}
-; CHECK: [[TBAA_STRUCT6]] = !{i64 0, i64 8, [[META7:![0-9]+]], i64 8, i64 4, [[META1]]}
-; CHECK: [[META7]] = !{[[META8:![0-9]+]], [[META8]], i64 0}
+; CHECK: [[TBAA_STRUCT5]] = !{i64 0, i64 4, [[TBAA1]]}
+; CHECK: [[TBAA_STRUCT6]] = !{i64 0, i64 8, [[TBAA7]], i64 8, i64 4, [[TBAA1]]}
+; CHECK: [[TBAA7]] = !{[[META8:![0-9]+]], [[META8]], i64 0}
; CHECK: [[META8]] = !{!"v2f32", [[META3]], i64 0}
-; CHECK: [[TBAA_STRUCT9]] = !{i64 0, i64 4, [[META1]], i64 4, i64 8, [[META7]]}
-; CHECK: [[TBAA_STRUCT10]] = !{i64 0, i64 8, [[META7]]}
-; CHECK: [[TBAA_STRUCT11]] = !{i64 0, i64 8, [[META7]], i64 4, i64 8, [[META1]]}
-; CHECK: [[TBAA_STRUCT12]] = !{i64 0, i64 2, [[META1]], i64 2, i64 6, [[META1]]}
-; CHECK: [[TBAA_STRUCT13]] = !{i64 0, i64 2, [[META1]]}
-; CHECK: [[TBAA_STRUCT14]] = !{i64 0, i64 7, [[META7]], i64 7, i64 1, [[META7]]}
-; CHECK: [[TBAA_STRUCT15]] = !{i64 0, i64 1, [[META7]]}
-; CHECK: [[TBAA_STRUCT16]] = !{i64 0, i64 2, [[META1]], i64 2, i64 2, [[META1]]}
-; CHECK: [[TBAA_STRUCT17]] = !{i64 0, i64 3, [[META1]]}
-; CHECK: [[TBAA_STRUCT18]] = !{i64 0, i64 1, [[META1]]}
-; CHECK: [[TBAA_STRUCT19]] = !{i64 0, i64 4, [[META7]]}
-; CHECK: [[TBAA_STRUCT20]] = !{i64 0, i64 2, [[META7]], i64 4, i64 4, [[META7]], i64 8, i64 1, [[META7]]}
-; CHECK: [[TBAA_STRUCT21]] = !{i64 0, i64 4, [[META7]], i64 4, i64 1, [[META7]]}
+; CHECK: [[TBAA_STRUCT9]] = !{i64 0, i64 4, [[TBAA1]], i64 4, i64 8, [[TBAA7]]}
+; CHECK: [[TBAA_STRUCT10]] = !{i64 0, i64 8, [[TBAA7]], i64 4, i64 8, [[TBAA1]]}
+; CHECK: [[TBAA_STRUCT11]] = !{i64 0, i64 2, [[TBAA1]], i64 2, i64 6, [[TBAA1]]}
+; CHECK: [[TBAA_STRUCT12]] = !{i64 0, i64 7, [[TBAA7]], i64 7, i64 1, [[TBAA7]]}
+; CHECK: [[TBAA_STRUCT13]] = !{i64 0, i64 2, [[TBAA1]], i64 2, i64 2, [[TBAA1]]}
+; CHECK: [[TBAA_STRUCT14]] = !{i64 0, i64 3, [[TBAA1]]}
+; CHECK: [[TBAA_STRUCT15]] = !{i64 0, i64 4, [[TBAA7]]}
+; CHECK: [[TBAA_STRUCT16]] = !{i64 0, i64 2, [[TBAA7]], i64 4, i64 4, [[TBAA7]], i64 8, i64 1, [[TBAA7]]}
+; CHECK: [[TBAA_STRUCT17]] = !{i64 0, i64 4, [[TBAA7]], i64 4, i64 1, [[TBAA7]]}
;.
diff --git a/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test b/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
index fc5856691f8dca..f88b7575002a94 100644
--- a/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
+++ b/llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
@@ -48,6 +48,9 @@
# RUN: llvm-objcopy -I binary -O elf64-loongarch %t.txt %t.la64.o
# RUN: llvm-readobj --file-headers %t.la64.o | FileCheck %s --check-prefixes=CHECK,LE,LA64,64
+# RUN: llvm-objcopy -I binary -O elf64-s390 %t.txt %t.s390x.o
+# RUN: llvm-readobj --file-headers %t.s390x.o | FileCheck %s --check-prefixes=CHECK,BE,S390X,64
+
# CHECK: Format:
# 32-SAME: elf32-
# 64-SAME: elf64-
@@ -64,6 +67,7 @@
# PPCLE-SAME: powerpcle{{$}}
# SPARC-SAME: sparc
# SPARCEL-SAME: sparc
+# S390X-SAME: s390
# X86-64-SAME: x86-64
# AARCH64-NEXT: Arch: aarch64
@@ -81,6 +85,7 @@
# RISCV64-NEXT: Arch: riscv64
# SPARC-NEXT: Arch: sparc{{$}}
# SPARCEL-NEXT: Arch: sparcel
+# S390X-NEXT: Arch: s390x
# X86-64-NEXT: Arch: x86_64
# 32-NEXT: AddressSize: 32bit
@@ -116,6 +121,7 @@
# RISCV64-NEXT: Machine: EM_RISCV (0xF3)
# SPARC-NEXT: Machine: EM_SPARC (0x2)
# SPARCEL-NEXT: Machine: EM_SPARC (0x2)
+# S390X-NEXT: Machine: EM_S390 (0x16)
# X86-64-NEXT: Machine: EM_X86_64 (0x3E)
# CHECK-NEXT: Version: 1
diff --git a/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test b/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test
index 882940c05e19c2..9a8128611792d5 100644
--- a/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test
+++ b/llvm/test/tools/llvm-objcopy/ELF/cross-arch-headers.test
@@ -117,6 +117,10 @@
# RUN: llvm-readobj --file-headers %t.elf64_loongarch.o | FileCheck %s --check-prefixes=CHECK,LE,LA64,64,SYSV
# RUN: llvm-readobj --file-headers %t.elf64_loongarch.dwo | FileCheck %s --check-prefixes=CHECK,LE,LA64,64,SYSV
+# RUN: llvm-objcopy %t.o -O elf64-s390 %t.elf64_s390.o --split-dwo=%t.elf64_s390.dwo
+# RUN: llvm-readobj --file-headers %t.elf64_s390.o | FileCheck %s --check-prefixes=CHECK,BE,S390X,64,SYSV
+# RUN: llvm-readobj --file-headers %t.elf64_s390.dwo | FileCheck %s --check-prefixes=CHECK,BE,S390X,64,SYSV
+
!ELF
FileHeader:
Class: ELFCLASS32
@@ -160,6 +164,7 @@ Symbols:
# RISCV32-SAME: riscv{{$}}
# RISCV64-SAME: riscv{{$}}
# SPARC-SAME: sparc
+# S390X-SAME: s390
# X86-64-SAME: x86-64
# DEFAULT-SAME: unknown
@@ -182,6 +187,7 @@ Symbols:
# RISCV64-NEXT: Arch: riscv64
# SPARC-NEXT: Arch: sparc{{$}}
# SPARCEL-NEXT: Arch: sparcel
+# S390X-NEXT: Arch: s390x
# X86-64-NEXT: Arch: x86_64
# DEFAULT-NEXT: Arch: unknown
@@ -210,6 +216,7 @@ Symbols:
# RISCV32: Machine: EM_RISCV (0xF3)
# RISCV64: Machine: EM_RISCV (0xF3)
# SPARC: Machine: EM_SPARC (0x2)
+# S390X: Machine: EM_S390 (0x16)
# X86-64: Machine: EM_X86_64 (0x3E)
# 32: HeaderSize: 52
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