[llvm] 3d81d48 - [InstCombine] Added additional funnel shift tests (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 16 07:49:26 PST 2024
Author: Eikansh Gupta
Date: 2024-02-16T16:48:55+01:00
New Revision: 3d81d48398f04119f568206d47a29dd6a96c4a08
URL: https://github.com/llvm/llvm-project/commit/3d81d48398f04119f568206d47a29dd6a96c4a08
DIFF: https://github.com/llvm/llvm-project/commit/3d81d48398f04119f568206d47a29dd6a96c4a08.diff
LOG: [InstCombine] Added additional funnel shift tests (NFC)
Added:
Modified:
llvm/test/Transforms/InstCombine/fsh.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/fsh.ll b/llvm/test/Transforms/InstCombine/fsh.ll
index 48bf296993f6ac..6ab47febb71405 100644
--- a/llvm/test/Transforms/InstCombine/fsh.ll
+++ b/llvm/test/Transforms/InstCombine/fsh.ll
@@ -722,6 +722,134 @@ define i32 @fsh_orconst_rotate(i32 %a) {
ret i32 %t2
}
+define i32 @fsh_rotate_5(i8 %x, i32 %y) {
+; CHECK-LABEL: @fsh_rotate_5(
+; CHECK-NEXT: [[T1:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[OR1:%.*]] = or i32 [[T1]], [[Y:%.*]]
+; CHECK-NEXT: [[OR2:%.*]] = call i32 @llvm.fshl.i32(i32 [[OR1]], i32 [[Y]], i32 5)
+; CHECK-NEXT: ret i32 [[OR2]]
+;
+
+ %t1 = zext i8 %x to i32
+ %or1 = or i32 %t1, %y
+ %shr = lshr i32 %or1, 27
+ %shl = shl i32 %or1, 5
+ %or2 = or i32 %shr, %shl
+ ret i32 %or2
+}
+
+define i32 @fsh_rotate_18(i8 %x, i32 %y) {
+; CHECK-LABEL: @fsh_rotate_18(
+; CHECK-NEXT: [[T1:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[OR1:%.*]] = or i32 [[T1]], [[Y:%.*]]
+; CHECK-NEXT: [[OR2:%.*]] = call i32 @llvm.fshl.i32(i32 [[OR1]], i32 [[Y]], i32 18)
+; CHECK-NEXT: ret i32 [[OR2]]
+;
+
+ %t1 = zext i8 %x to i32
+ %or1 = or i32 %t1, %y
+ %shr = lshr i32 %or1, 14
+ %shl = shl i32 %or1, 18
+ %or2 = or i32 %shr, %shl
+ ret i32 %or2
+}
+
+define i32 @fsh_load_rotate_12(ptr %data) {
+; CHECK-LABEL: @fsh_load_rotate_12(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[DATA:%.*]], align 1
+; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
+; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[CONV]], 24
+; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 1
+; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1
+; CHECK-NEXT: [[CONV2:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT: [[SHL3:%.*]] = shl nuw nsw i32 [[CONV2]], 16
+; CHECK-NEXT: [[OR:%.*]] = or disjoint i32 [[SHL3]], [[SHL]]
+; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 2
+; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
+; CHECK-NEXT: [[CONV5:%.*]] = zext i8 [[TMP2]] to i32
+; CHECK-NEXT: [[SHL6:%.*]] = shl nuw nsw i32 [[CONV5]], 8
+; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 3
+; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1
+; CHECK-NEXT: [[CONV9:%.*]] = zext i8 [[TMP3]] to i32
+; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[SHL6]], [[CONV9]]
+; CHECK-NEXT: [[OR10:%.*]] = or disjoint i32 [[TMP4]], [[SHL3]]
+; CHECK-NEXT: [[OR15:%.*]] = call i32 @llvm.fshl.i32(i32 [[OR10]], i32 [[OR]], i32 12)
+; CHECK-NEXT: ret i32 [[OR15]]
+;
+
+entry:
+ %0 = load i8, ptr %data
+ %conv = zext i8 %0 to i32
+ %shl = shl nuw i32 %conv, 24
+ %arrayidx1 = getelementptr inbounds i8, ptr %data, i64 1
+ %1 = load i8, ptr %arrayidx1
+ %conv2 = zext i8 %1 to i32
+ %shl3 = shl nuw nsw i32 %conv2, 16
+ %or = or i32 %shl3, %shl
+ %arrayidx4 = getelementptr inbounds i8, ptr %data, i64 2
+ %2 = load i8, ptr %arrayidx4
+ %conv5 = zext i8 %2 to i32
+ %shl6 = shl nuw nsw i32 %conv5, 8
+ %or7 = or i32 %or, %shl6
+ %arrayidx8 = getelementptr inbounds i8, ptr %data, i64 3
+ %3 = load i8, ptr %arrayidx8
+ %conv9 = zext i8 %3 to i32
+ %or10 = or i32 %or7, %conv9
+ %shr = lshr i32 %or10, 20
+ %shl7 = shl i32 %or10, 12
+ %or15 = or i32 %shr, %shl7
+ ret i32 %or15
+}
+
+define i32 @fsh_load_rotate_25(ptr %data) {
+; CHECK-LABEL: @fsh_load_rotate_25(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[DATA:%.*]], align 1
+; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32
+; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[CONV]], 24
+; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 1
+; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1
+; CHECK-NEXT: [[CONV2:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT: [[SHL3:%.*]] = shl nuw nsw i32 [[CONV2]], 16
+; CHECK-NEXT: [[OR:%.*]] = or disjoint i32 [[SHL3]], [[SHL]]
+; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 2
+; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1
+; CHECK-NEXT: [[CONV5:%.*]] = zext i8 [[TMP2]] to i32
+; CHECK-NEXT: [[SHL6:%.*]] = shl nuw nsw i32 [[CONV5]], 8
+; CHECK-NEXT: [[OR7:%.*]] = or disjoint i32 [[OR]], [[SHL6]]
+; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 3
+; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1
+; CHECK-NEXT: [[CONV9:%.*]] = zext i8 [[TMP3]] to i32
+; CHECK-NEXT: [[OR10:%.*]] = or disjoint i32 [[OR7]], [[CONV9]]
+; CHECK-NEXT: [[OR15:%.*]] = call i32 @llvm.fshl.i32(i32 [[CONV9]], i32 [[OR10]], i32 25)
+; CHECK-NEXT: ret i32 [[OR15]]
+;
+
+entry:
+ %0 = load i8, ptr %data
+ %conv = zext i8 %0 to i32
+ %shl = shl nuw i32 %conv, 24
+ %arrayidx1 = getelementptr inbounds i8, ptr %data, i64 1
+ %1 = load i8, ptr %arrayidx1
+ %conv2 = zext i8 %1 to i32
+ %shl3 = shl nuw nsw i32 %conv2, 16
+ %or = or i32 %shl3, %shl
+ %arrayidx4 = getelementptr inbounds i8, ptr %data, i64 2
+ %2 = load i8, ptr %arrayidx4
+ %conv5 = zext i8 %2 to i32
+ %shl6 = shl nuw nsw i32 %conv5, 8
+ %or7 = or i32 %or, %shl6
+ %arrayidx8 = getelementptr inbounds i8, ptr %data, i64 3
+ %3 = load i8, ptr %arrayidx8
+ %conv9 = zext i8 %3 to i32
+ %or10 = or i32 %or7, %conv9
+ %shr = lshr i32 %or10, 7
+ %shl7 = shl i32 %or10, 25
+ %or15 = or i32 %shr, %shl7
+ ret i32 %or15
+}
+
define <2 x i31> @fshr_mask_args_same_vector(<2 x i31> %a) {
; CHECK-LABEL: @fshr_mask_args_same_vector(
; CHECK-NEXT: [[T3:%.*]] = shl <2 x i31> [[A:%.*]], <i31 10, i31 10>
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