[llvm] [GlobalISel][TableGen] Take first result for multi-output instructions (PR #81130)

[Björn Pettersson via llvm-commits]

bjope wrote:

Yes, given this patch at least the test/CodeGen/AMDGPU lit tests still pass even if I remove the selectG_FABS/G_FNEG helpers. So this will import tablegen patterns that now are triggered instead.

For example these patterns in SIInstructions.td:
```
// FIXME: Use S_BITSET0_B32/B64?
def : GCNPat <
  (UniformUnaryFrag<fabs> (f64 SReg_64:$src)),
  (REG_SEQUENCE SReg_64,
    (i32 (EXTRACT_SUBREG SReg_64:$src, sub0)),
    sub0,
    (i32 (COPY_TO_REGCLASS (S_AND_B32 (i32 (EXTRACT_SUBREG SReg_64:$src, sub1)),
                   (S_MOV_B32 (i32 0x7fffffff))), SReg_32)), // Set sign bit.
     sub1)
>;

def : GCNPat <
  (UniformUnaryFrag<fneg> (f64 SReg_64:$src)),
  (REG_SEQUENCE SReg_64,
    (i32 (EXTRACT_SUBREG SReg_64:$src, sub0)),
    sub0,
    (i32 (COPY_TO_REGCLASS (S_XOR_B32 (i32 (EXTRACT_SUBREG SReg_64:$src, sub1)),
                   (i32 (S_MOV_B32 (i32 0x80000000)))), SReg_32)),
    sub1)
>;
```

For some reason those are implemented to give a different lowering compared to the AMDGPUInstructionSelector workarounds that seem to have been added due to failing to import those patterns earlier.

However, for example AMDGPUInstructionSelector::selectG_FNEG talks about 2.5 different tablgen problems. So maybe there is some other reasons for not using the tablegen patterns? Then I guess someone working with AMDGPU can disable the non-profitable/bad tablegen patterns instead.

https://github.com/llvm/llvm-project/pull/81130