[llvm] [AMDGPU] Consolidate SGPRSpill and VGPRSpill into single Spill bit (PR #81901)

[Jay Foad via llvm-commits]

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@@ -87,9 +87,9 @@ enum : uint64_t {
   FLAT = 1 << 24,
   DS = 1 << 25,
 
-  // Pseudo instruction formats.
-  VGPRSpill = 1 << 26,
-  SGPRSpill = 1 << 27,
+  // Combined SGPR/VGPR Spill bit
+  // logic to seperate them out is done in isSGPRSpill and isVGPRSpill
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jayfoad wrote:

Capitalise "Logic" or write it as a complete sentence (per coding standards). Typo "separate".

https://github.com/llvm/llvm-project/pull/81901