[llvm] [AMDGPU] Consolidate SGPRSpill and VGPRSpill into single Spill bit (PR #81901)

[via llvm-commits]

github-actions[bot] wrote:

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``````````bash
git-clang-format --diff 08fe7df600aeff45917eb865d103d6c431f42285 917929482b7208e9c23993b021a2f4842ae8b440 -- llvm/lib/Target/AMDGPU/SIDefines.h llvm/lib/Target/AMDGPU/SIInstrInfo.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.h
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 11e011ca0d..8717841e19 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -8814,7 +8814,7 @@ bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI,
   // be included.
   return IsNullOrVectorRegister &&
          (isSpill(Opcode) || (!MI.isTerminator() && Opcode != AMDGPU::COPY &&
-                                 MI.modifiesRegister(AMDGPU::EXEC, &RI)));
+                              MI.modifiesRegister(AMDGPU::EXEC, &RI)));
 }
 
 MachineInstrBuilder
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index a887eccf08..f6d9862d27 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -716,25 +716,25 @@ public:
   static bool isVGPRSpill(const MachineInstr &MI) {
     return MI.getOpcode() != AMDGPU::SI_SPILL_S32_TO_VGPR &&
            MI.getOpcode() != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
-		   (isSpill(MI) & isVALU(MI));
+           (isSpill(MI) & isVALU(MI));
   }
 
   bool isVGPRSpill(uint16_t Opcode) const {
     return Opcode != AMDGPU::SI_SPILL_S32_TO_VGPR &&
            Opcode != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
-		   (isSpill(Opcode) & isVALU(Opcode));
+           (isSpill(Opcode) & isVALU(Opcode));
   }
 
   static bool isSGPRSpill(const MachineInstr &MI) {
     return MI.getOpcode() == AMDGPU::SI_SPILL_S32_TO_VGPR ||
            MI.getOpcode() == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
-		   (isSpill(MI) & isSALU(MI));
+           (isSpill(MI) & isSALU(MI));
   }
 
   bool isSGPRSpill(uint16_t Opcode) const {
     return Opcode == AMDGPU::SI_SPILL_S32_TO_VGPR ||
            Opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
-	       (isSpill(Opcode) & isSALU(Opcode));
+           (isSpill(Opcode) & isSALU(Opcode));
   }
 
   bool isSpill(uint16_t Opcode) const {
@@ -742,7 +742,7 @@ public:
   }
 
   static bool isSpill(const MachineInstr &MI) {
-	return MI.getDesc().TSFlags & SIInstrFlags::Spill;
+    return MI.getDesc().TSFlags & SIInstrFlags::Spill;
   }
 
   static bool isWWMRegSpillOpcode(uint16_t Opcode) {

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https://github.com/llvm/llvm-project/pull/81901