[llvm] [AMDGPU] Rewrite `getVregSrcForVT` with `!cond` (PR #81954)
Shilei Tian via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 15 17:07:56 PST 2024
https://github.com/shiltian created https://github.com/llvm/llvm-project/pull/81954
None
>From 658d283e6c99a748db95ed6f3905d524687f5828 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Thu, 15 Feb 2024 20:05:13 -0500
Subject: [PATCH] [AMDGPU] Rewrite `getVregSrcForVT` with `!cond`
---
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 4b7555de712c80..c0c1caeca59840 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1528,15 +1528,14 @@ class getSOPSrcForVT<ValueType VT> {
// Returns the vreg register class to use for source operand given VT
class getVregSrcForVT<ValueType VT, bit IsTrue16 = 0, bit IsFake16 = 0> {
RegisterOperand ret =
- !if (!eq(VT.Size, 128), RegisterOperand<VReg_128>,
- !if (!eq(VT.Size, 96), RegisterOperand<VReg_96>,
- !if (!eq(VT.Size, 64), RegisterOperand<VReg_64>,
- !if (!eq(VT.Size, 48), RegisterOperand<VReg_64>,
- !if (!eq(VT.Size, 16),
- !if (IsTrue16,
- !if (IsFake16, VGPRSrc_32_Lo128, VGPRSrc_16_Lo128),
- RegisterOperand<VGPR_32>),
- RegisterOperand<VGPR_32>)))));
+ !cond(!eq(VT.Size, 128) : RegisterOperand<VReg_128>,
+ !eq(VT.Size, 96) : RegisterOperand<VReg_96>,
+ !eq(VT.Size, 64) : RegisterOperand<VReg_64>,
+ !eq(VT.Size, 48) : RegisterOperand<VReg_64>,
+ !eq(VT.Size, 16) : !if(IsTrue16,
+ !if(IsFake16, VGPRSrc_32_Lo128, VGPRSrc_16_Lo128),
+ RegisterOperand<VGPR_32>),
+ 1 : RegisterOperand<VGPR_32>);
}
class getSDWASrcForVT <ValueType VT> {
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