[llvm] 55b5ac8 - [RISCV] Remove X0 handling from RISCVInstrInfo::optimizeCondBranch. (#81931)

[via llvm-commits]

Author: Craig Topper
Date: 2024-02-15T16:45:54-08:00
New Revision: 55b5ac8917b4a1e0ceb79bee4c4c6f7d35b95526

URL: https://github.com/llvm/llvm-project/commit/55b5ac8917b4a1e0ceb79bee4c4c6f7d35b95526
DIFF: https://github.com/llvm/llvm-project/commit/55b5ac8917b4a1e0ceb79bee4c4c6f7d35b95526.diff

LOG: [RISCV] Remove X0 handling from RISCVInstrInfo::optimizeCondBranch. (#81931)

This was trying to rewrite a branch that uses X0 to a branch that uses a
register produced by LI of 1 or -1. Using X0 is free so there is no
reason to rewrite it. Doing so would just extend the live range of the
LI register increasing register pressure.

In practice this might not have triggered often because we were calling
MRI.hasOneUse on X0. I'm not sure what the returns for a physical
reigster.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index af7c40d0ca1ec6..2abe015c9f9cdc 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1211,13 +1211,7 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const {
     if (!Op.isReg())
       return false;
     Register Reg = Op.getReg();
-    if (Reg == RISCV::X0) {
-      Imm = 0;
-      return true;
-    }
-    if (!Reg.isVirtual())
-      return false;
-    return isLoadImm(MRI.getVRegDef(Op.getReg()), Imm);
+    return Reg.isVirtual() && isLoadImm(MRI.getVRegDef(Reg), Imm);
   };
 
   MachineOperand &LHS = MI.getOperand(0);