[clang] [llvm] [AMDGPU] Emit a waitcnt instruction after each memory instruction (PR #79236)

[Jun Wang via llvm-commits]

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@@ -603,14 +626,69 @@ class SIGfx12CacheControl : public SIGfx11CacheControl {
                                       SIAtomicAddrSpace AddrSpace, SIMemOp Op,
                                       bool IsVolatile,
                                       bool IsNonTemporal) const override;
+
+  bool
+  handleNonAtomicForPreciseMemory(MachineBasicBlock::iterator &MI) override;
+  bool handleAtomicForPreciseMemory(MachineBasicBlock::iterator &MI,
+                                    bool ret) override;
+};
+
+#if 0
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jwanggit86 wrote:

Regarding the question about SIInsertWaitcnt, initially the code was indeed put there (see PR [68932](https://github.com/llvm/llvm-project/pull/68932)). After a discussion with @t-tye and others, it was decided to do it in SIMemoryLegalizer. I think the main reason is that functionality-wise this new feather is more closely related to the Mem Legalizer. Tony can explain this better. Also, the Mem Legalizer, like SIInsertWaitcnt, goes through each instruction already.
Based on the implementation experience, I'd say another reason that supports putting it in the Mem Legalizer is that there's already a class hierarchy for the different ISAs, making it easier to implement ISA-specific behaviors.

https://github.com/llvm/llvm-project/pull/79236