[llvm] [AMDGPU] Consolidate SGPRSpill and VGPRSpill into single Spill bit (PR #81901)
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 15 11:53:30 PST 2024
================
@@ -708,25 +708,41 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
}
+ // SI_SPILL_S32_TO_VGPR and SI_RESTORE_S32_FROM_VGPR form a special case of
+ // SGPRs spilling to VGPRs which are SGPR spills but from VALU instructions
+ // therefore we need an explicit check for them since just checking if the
+ // Spill bit is set and what instruction type it came from misclassifies
+ // them.
static bool isVGPRSpill(const MachineInstr &MI) {
- return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
+ return MI.getOpcode() != AMDGPU::SI_SPILL_S32_TO_VGPR &&
+ MI.getOpcode() != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
+ ((MI.getDesc().TSFlags & SIInstrFlags::Spill) &&
+ (MI.getDesc().TSFlags & SIInstrFlags::VALU));
----------------
rampitec wrote:
You can just use isVALU(MI). Then also add isSpill(MI) helper and use it it here.
https://github.com/llvm/llvm-project/pull/81901
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