[llvm] [AArch64] Remove copy in SVE/SME predicate spill (PR #81716)

[Sam Tebbs via llvm-commits]

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@@ -4807,8 +4808,9 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
              "Unexpected register store without SVE2p1 or SME2");
       if (SrcReg.isVirtual()) {
         auto NewSrcReg =
-            MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass);
-        BuildMI(MBB, MBBI, DebugLoc(), get(TargetOpcode::COPY), NewSrcReg)
+            MF.getRegInfo().createVirtualRegister(&AArch64::PPR_p8to15RegClass);
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SamTebbs33 wrote:

Changing the source register to p8to15 gives it the chance to overlap with the whilege in the test. Without this change the source register will be allocated to p0, as that is the first register in the PPR register class's allocation order, and we can't elide the copy. If anyone else can think of a better approach to get regalloc to make the convert and whilege share registers (e.g. p8 and pn8 respectively), please do mention it.

https://github.com/llvm/llvm-project/pull/81716