[llvm] 94f5164 - [LLVM][X86] Add EFLAGS Defs for VERR/VERW instructions (#81824)

[via llvm-commits]

Author: riChar
Date: 2024-02-15T14:04:53+08:00
New Revision: 94f51649c4a574f88fd9b8a2d0a05b334c0bd490

URL: https://github.com/llvm/llvm-project/commit/94f51649c4a574f88fd9b8a2d0a05b334c0bd490
DIFF: https://github.com/llvm/llvm-project/commit/94f51649c4a574f88fd9b8a2d0a05b334c0bd490.diff

LOG: [LLVM][X86] Add EFLAGS Defs for VERR/VERW instructions (#81824)

VERR/VERW instructions will define ZF flag.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86InstrSystem.td

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td
index 24a334d38f9261..d051047ae46548 100644
--- a/llvm/lib/Target/X86/X86InstrSystem.td
+++ b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -366,12 +366,14 @@ def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
                  "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
 
+let Defs = [EFLAGS] in {
 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB;
 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB;
 let mayLoad = 1 in {
 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB;
 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB;
 }
+} // Defs EFLAGS
 } // SchedRW
 
 //===----------------------------------------------------------------------===//