================
@@ -25008,6 +25008,16 @@ void AArch64TargetLowering::ReplaceNodeResults(
Results.push_back(
LowerToPredicatedOp(SDValue(N, 0), DAG, AArch64ISD::MULHU_PRED));
return;
+ case ISD::FP_ROUND: {
----------------
nasherm wrote:
Using a generic legalizer we run into the following:
```=== f2h
Initial selection DAG: %bb.0 'f2h:entry'
SelectionDAG has 11 nodes:
t0: ch,glue = EntryToken
t2: i32,ch = CopyFromReg t0, Register:i32 %0
t3: f32 = bitcast t2
t5: f16 = fp_round t3, TargetConstant:i64<0>
t6: i16 = bitcast t5
t7: i32 = any_extend t6
t9: ch,glue = CopyToReg t0, Register:i32 $w0, t7
t10: ch = AArch64ISD::RET_GLUE t9, Register:i32 $w0, t9:1
Optimized lowered selection DAG: %bb.0 'f2h:entry'
SelectionDAG has 11 nodes:
t0: ch,glue = EntryToken
t2: i32,ch = CopyFromReg t0, Register:i32 %0
t3: f32 = bitcast t2
t5: f16 = fp_round t3, TargetConstant:i64<0>
t6: i16 = bitcast t5
t7: i32 = any_extend t6
t9: ch,glue = CopyToReg t0, Register:i32 $w0, t7
t10: ch = AArch64ISD::RET_GLUE t9, Register:i32 $w0, t9:1
SoftenFloatResult #0: t15: f32 = INSERT_SUBREG undef:i32, t5, TargetConstant:i32<7>
LLVM ERROR: Do not know how to soften the result of this operator! ```
After investigating a bit it appears that INSERT_SUBREG is an MIR instruction that is used to implement `any_extend`. This is confusing to me as I wouldn't expect the DAG to try and legalize an MIR instruction. Am I right in thinking this is a bug?
https://github.com/llvm/llvm-project/pull/81724