[llvm] [AArch64][SVE] Instcombine uzp1/reinterpret svbool to use vector.insert (PR #81069)

[Paul Walker via llvm-commits]

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@@ -0,0 +1,177 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -S -passes=instcombine -mtriple=aarch64 < %s | FileCheck %s
+
+; Code the concatenates two predictes using uzp1 after converting to
+; double length using sve.convert.to/from.svbool is optimized poorly
+; in the backend, resulting in additional `and` instructions to zero
+; the lanes. Test that we get rid of convert to/from and generate a
+; concatenate using vector insert instead.
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paulwalker-arm wrote:

Not sure it's worth critiquing the code generator here.  Perhaps keep it simple, something like "Transform the SVE idiom used to concatenate two vectors into target agnostic IR"?

https://github.com/llvm/llvm-project/pull/81069