[llvm] [AArch64] Add Ampere1B scheduling/pipeline model (PR #81341)

[Philipp Tomsich via llvm-commits]

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@@ -0,0 +1,1063 @@
+//=- AArch64SchedAmpere1B.td - Ampere-1B scheduling def -----*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for the Ampere Computing Ampere-1B to
+// support instruction scheduling and other instruction cost heuristics.
+//
+//===----------------------------------------------------------------------===//
+
+// The Ampere-1 core is an out-of-order micro-architecture.  The front
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ptomsich wrote:

While the core naming by Ampere looks like 1/1A/1B are minor updates, this is not the case (at least every other core is a major update).  There is some low-priority work planned to improve the 1/1A model (e.g., MTE was added with 1A but is not modelled) in the LLVM19 timeframe, but the focus is on 1B.

https://github.com/llvm/llvm-project/pull/81341