[llvm] [AArch64][CodeGen] Fix crash when fptrunc returns fp16 with +nofp attr (PR #81724)

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git-clang-format --diff 124cd11d7f9d875b7d6dd441dc758ed9341ccec2 6c7a740bf0004d97d7c8bebd15c4a878db6bdcc7 -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index c58600ae38..a82bd77cce 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -25008,12 +25008,13 @@ void AArch64TargetLowering::ReplaceNodeResults(
       Results.push_back(
           LowerToPredicatedOp(SDValue(N, 0), DAG, AArch64ISD::MULHU_PRED));
     return;
-  case ISD::FP_ROUND:{
+  case ISD::FP_ROUND: {
     if (N->getValueType(0) == MVT::f16 && !Subtarget->hasFullFP16()) {
-        // Promote fp16 result to legal type
-        SDLoc DL(N);
-        EVT NVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
-        Results.push_back(DAG.getNode(ISD::FP16_TO_FP, DL, NVT, N->getOperand(0)));
+      // Promote fp16 result to legal type
+      SDLoc DL(N);
+      EVT NVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+      Results.push_back(
+          DAG.getNode(ISD::FP16_TO_FP, DL, NVT, N->getOperand(0)));
     }
     return;
   }

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https://github.com/llvm/llvm-project/pull/81724