[llvm] [RISCV] Use SelectionDAG::getVScale in lowerVPReverseExperimental. NFCI (PR #81694)
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Tue Feb 13 19:24:22 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Luke Lau (lukel97)
<details>
<summary>Changes</summary>
Use a slightly more idiomatic way of getting vscale. getVScale
performs additional constant folding, but I presume computeKnownBits
also catches these cases too.
---
Full diff: https://github.com/llvm/llvm-project/pull/81694.diff
1 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+2-2)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 73492c28815b1d..4caadef694d725 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11106,8 +11106,8 @@ RISCVTargetLowering::lowerVPReverseExperimental(SDValue Op,
// Slide off any elements from past EVL that were reversed into the low
// elements.
unsigned MinElts = GatherVT.getVectorMinNumElements();
- SDValue VLMax = DAG.getNode(ISD::VSCALE, DL, XLenVT,
- DAG.getConstant(MinElts, DL, XLenVT));
+ SDValue VLMax =
+ DAG.getVScale(DL, XLenVT, APInt(XLenVT.getSizeInBits(), MinElts));
SDValue Diff = DAG.getNode(ISD::SUB, DL, XLenVT, VLMax, EVL);
Result = getVSlidedown(DAG, Subtarget, DL, GatherVT,
``````````
</details>
https://github.com/llvm/llvm-project/pull/81694
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