[llvm] a7cebad - [TableGen] Trivial simplification in computeRegUnitSets. NFC.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2024-02-13T17:16:25Z
New Revision: a7cebadc10948ca1b9df1a740370f8ef7cef7e77

URL: https://github.com/llvm/llvm-project/commit/a7cebadc10948ca1b9df1a740370f8ef7cef7e77
DIFF: https://github.com/llvm/llvm-project/commit/a7cebadc10948ca1b9df1a740370f8ef7cef7e77.diff

LOG: [TableGen] Trivial simplification in computeRegUnitSets. NFC.

Added: 
    

Modified: 
    llvm/utils/TableGen/CodeGenRegisters.cpp

Removed: 
    


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diff  --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index e29bc50118f0e6..7d266c8896d8e3 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -2107,10 +2107,8 @@ void CodeGenRegBank::computeRegUnitSets() {
        ++UnitIdx) {
     std::vector<unsigned> RUSets;
     for (unsigned i = 0, e = RegUnitSets.size(); i != e; ++i) {
-      RegUnitSet &RUSet = RegUnitSets[i];
-      if (!is_contained(RUSet.Units, UnitIdx))
-        continue;
-      RUSets.push_back(i);
+      if (is_contained(RegUnitSets[i].Units, UnitIdx))
+        RUSets.push_back(i);
     }
     unsigned RCUnitSetsIdx = 0;
     for (unsigned e = RegClassUnitSets.size(); RCUnitSetsIdx != e;