[llvm] [CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (PR #77770)

[via llvm-commits]

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@@ -1173,6 +1173,14 @@ class TargetRegisterInfo : public MCRegisterInfo {
   virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const {
     return false;
   }
+
+  /// Returns the Register Class that is being initialized. There
+  /// should be a Pseudo Instruction for the different register
+  /// classes for the different register types that are introduced.
+  virtual const TargetRegisterClass *
+  getTargetRegisterClass(const TargetRegisterClass *RC) const {
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ostannard wrote:

This name doesn't make much sense, and the comment doesn't clarify things. How about `getLargestSuperClass`?

https://github.com/llvm/llvm-project/pull/77770